Finish migrating from the old symbol to the new one.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
12 files changed:
static int arm720t_arch_state(struct target *target)
{
struct arm720t_common *arm720t = target_to_arm720(target);
static int arm720t_arch_state(struct target *target)
{
struct arm720t_common *arm720t = target_to_arm720(target);
- struct armv4_5_common_s *armv4_5;
static const char *state[] =
{
static const char *state[] =
{
struct arm720t_common *arm720t = target_to_arm720(target);
struct reg *dbg_stat = &arm720t->arm7_9_common
.eice_cache->reg_list[EICE_DBG_STAT];
struct arm720t_common *arm720t = target_to_arm720(target);
struct reg *dbg_stat = &arm720t->arm7_9_common
.eice_cache->reg_list[EICE_DBG_STAT];
- struct armv4_5_common_s *armv4_5 = &arm720t->arm7_9_common
+ struct arm *armv4_5 = &arm720t->arm7_9_common
.armv4_5_common;
if ((retval = target_halt(target)) != ERROR_OK)
.armv4_5_common;
if ((retval = target_halt(target)) != ERROR_OK)
int arm7_9_soft_reset_halt(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int arm7_9_soft_reset_halt(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int i;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int i;
uint32_t cpsr, cpsr_mask = 0;
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
uint32_t cpsr, cpsr_mask = 0;
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int i;
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int i;
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
int arm7_9_restore_context(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int arm7_9_restore_context(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *reg;
struct arm_reg *reg_arch_info;
enum armv4_5_mode current_mode = armv4_5->core_mode;
struct reg *reg;
struct arm_reg *reg_arch_info;
enum armv4_5_mode current_mode = armv4_5->core_mode;
int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct breakpoint *breakpoint = target->breakpoints;
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int err, retval = ERROR_OK;
struct breakpoint *breakpoint = target->breakpoints;
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int err, retval = ERROR_OK;
void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
uint32_t current_pc;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
uint32_t current_pc;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct breakpoint *breakpoint = NULL;
int err, retval;
struct breakpoint *breakpoint = NULL;
int err, retval;
int retval;
struct arm_reg *areg = r->arch_info;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int retval;
struct arm_reg *areg = r->arch_info;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
uint32_t reg[16];
struct arm_reg *areg = r->arch_info;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
uint32_t reg[16];
struct arm_reg *areg = r->arch_info;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
uint32_t reg[16];
uint32_t num_accesses = 0;
int thisrun_accesses;
uint32_t reg[16];
uint32_t num_accesses = 0;
int thisrun_accesses;
int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
uint32_t reg[16];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
uint32_t reg[16];
static void arm7tdmi_branch_resume_thumb(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static void arm7tdmi_branch_resume_thumb(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
static void arm7tdmi_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
static void arm7tdmi_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
}
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
}
static int arm920t_read_cp15_interpreted(struct target *target,
uint32_t cp15_opcode, uint32_t address, uint32_t *value)
{
static int arm920t_read_cp15_interpreted(struct target *target,
uint32_t cp15_opcode, uint32_t address, uint32_t *value)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
uint32_t* regs_p[1];
uint32_t regs[2];
uint32_t cp15c15 = 0x0;
uint32_t* regs_p[1];
uint32_t regs[2];
uint32_t cp15c15 = 0x0;
uint32_t cp15_opcode, uint32_t value, uint32_t address)
{
uint32_t cp15c15 = 0x0;
uint32_t cp15_opcode, uint32_t value, uint32_t address)
{
uint32_t cp15c15 = 0x0;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
uint32_t regs[2];
/* load value, address into R0, R1 */
uint32_t regs[2];
/* load value, address into R0, R1 */
};
struct arm920t_common *arm920t = target_to_arm920(target);
};
struct arm920t_common *arm920t = target_to_arm920(target);
- struct armv4_5_common_s *armv4_5;
if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
{
if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
{
int retval = ERROR_OK;
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int retval = ERROR_OK;
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK)
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK)
struct target *target = get_current_target(CMD_CTX);
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct target *target = get_current_target(CMD_CTX);
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16];
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16];
struct target *target = get_current_target(CMD_CTX);
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct target *target = get_current_target(CMD_CTX);
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16];
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16];
};
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
};
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
- struct armv4_5_common_s *armv4_5;
if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
{
if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
{
int retval = ERROR_OK;
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int retval = ERROR_OK;
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK)
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK)
LOG_DEBUG("-");
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
LOG_DEBUG("-");
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
static void arm9tdmi_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
static void arm9tdmi_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
}
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
}
int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
{
int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
struct arm_sim_interface sim;
sim.user_data = armv4_5;
struct arm_sim_interface sim;
sim.user_data = armv4_5;
{
struct arm_reg *armv4_5 = reg->arch_info;
struct target *target = armv4_5->target;
{
struct arm_reg *armv4_5 = reg->arch_info;
struct target *target = armv4_5->target;
- struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target);
+ struct arm *armv4_5_target = target_to_armv4_5(target);
uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED)
uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED)
int armv4_5_arch_state(struct target *target)
{
int armv4_5_arch_state(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
COMMAND_HANDLER(handle_armv4_5_reg_command)
{
struct target *target = get_current_target(CMD_CTX);
COMMAND_HANDLER(handle_armv4_5_reg_command)
{
struct target *target = get_current_target(CMD_CTX);
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
unsigned num_regs;
struct reg *regs;
unsigned num_regs;
struct reg *regs;
COMMAND_HANDLER(handle_armv4_5_core_state_command)
{
struct target *target = get_current_target(CMD_CTX);
COMMAND_HANDLER(handle_armv4_5_core_state_command)
{
struct target *target = get_current_target(CMD_CTX);
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{
int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
int i;
if (!is_arm_mode(armv4_5->core_mode))
int i;
if (!is_arm_mode(armv4_5->core_mode))
static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval;
static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
{
if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
{
int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info))
{
int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info))
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
uint32_t context[17];
struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
uint32_t context[17];
static int arm_full_context(struct target *target)
{
static int arm_full_context(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
unsigned num_regs = armv4_5->core_cache->num_regs;
struct reg *reg = armv4_5->core_cache->reg_list;
int retval = ERROR_OK;
unsigned num_regs = armv4_5->core_cache->num_regs;
struct reg *reg = armv4_5->core_cache->reg_list;
int retval = ERROR_OK;
#define ARMV4_5_COMMON_MAGIC 0x0A450A45
#define ARMV4_5_COMMON_MAGIC 0x0A450A45
-/* NOTE: this is being morphed into a generic toplevel holder for ARMs. */
-#define armv4_5_common_s arm
-
/**
* Represents a generic ARM core, with standard application registers.
*
/**
* Represents a generic ARM core, with standard application registers.
*
};
struct armv7a_common *armv7a = target_to_armv7a(target);
};
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+ struct arm *armv4_5 = &armv7a->armv4_5_common;
if (armv7a->common_magic != ARMV7_COMMON_MAGIC)
{
if (armv7a->common_magic != ARMV7_COMMON_MAGIC)
{
uint32_t address, int handle_breakpoints, int debug_execution)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
uint32_t address, int handle_breakpoints, int debug_execution)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+ struct arm *armv4_5 = &armv7a->armv4_5_common;
struct swjdp_common *swjdp = &armv7a->swjdp_info;
// struct breakpoint *breakpoint = NULL;
struct swjdp_common *swjdp = &armv7a->swjdp_info;
// struct breakpoint *breakpoint = NULL;
struct working_area *regfile_working_area = NULL;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct working_area *regfile_working_area = NULL;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+ struct arm *armv4_5 = &armv7a->armv4_5_common;
struct swjdp_common *swjdp = &armv7a->swjdp_info;
struct reg *reg;
struct swjdp_common *swjdp = &armv7a->swjdp_info;
struct reg *reg;
int handle_breakpoints)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
int handle_breakpoints)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+ struct arm *armv4_5 = &armv7a->armv4_5_common;
struct breakpoint *breakpoint = NULL;
struct breakpoint stepbreakpoint;
struct breakpoint *breakpoint = NULL;
struct breakpoint stepbreakpoint;
armv4_5_mode_t mode, uint32_t * value)
{
int retval;
armv4_5_mode_t mode, uint32_t * value)
{
int retval;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
{
int retval;
// uint32_t reg;
{
int retval;
// uint32_t reg;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
#ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us
#ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us
{
uint32_t value;
int retval;
{
uint32_t value;
int retval;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
struct reg *cpsr_r = NULL;
uint32_t cpsr = 0;
unsigned cookie = num;
struct reg *cpsr_r = NULL;
uint32_t cpsr = 0;
unsigned cookie = num;
int num, enum armv4_5_mode mode, uint32_t value)
{
int retval;
int num, enum armv4_5_mode mode, uint32_t value)
{
int retval;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
struct reg *cpsr_r = NULL;
uint32_t cpsr = 0;
unsigned cookie = num;
struct reg *cpsr_r = NULL;
uint32_t cpsr = 0;
unsigned cookie = num;
static void cortex_a8_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
static void cortex_a8_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
armv4_5->core_type = ARM_MODE_MON;
armv4_5->core_type = ARM_MODE_MON;
static int xscale_arch_state(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
static int xscale_arch_state(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
static const char *state[] =
{
static const char *state[] =
{
static int xscale_debug_entry(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
static int xscale_debug_entry(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
uint32_t pc;
uint32_t buffer[10];
int i;
uint32_t pc;
uint32_t buffer[10];
int i;
uint32_t address, int handle_breakpoints, int debug_execution)
{
struct xscale_common *xscale = target_to_xscale(target);
uint32_t address, int handle_breakpoints, int debug_execution)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
struct breakpoint *breakpoint = target->breakpoints;
uint32_t current_pc;
int retval;
struct breakpoint *breakpoint = target->breakpoints;
uint32_t current_pc;
int retval;
uint32_t address, int handle_breakpoints)
{
struct xscale_common *xscale = target_to_xscale(target);
uint32_t address, int handle_breakpoints)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
uint32_t next_pc;
int retval;
int i;
uint32_t next_pc;
int retval;
int i;
static int xscale_step(struct target *target, int current,
uint32_t address, int handle_breakpoints)
{
static int xscale_step(struct target *target, int current,
uint32_t address, int handle_breakpoints)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
struct breakpoint *breakpoint = target->breakpoints;
uint32_t current_pc;
struct breakpoint *breakpoint = target->breakpoints;
uint32_t current_pc;
static int xscale_full_context(struct target *target)
{
static int xscale_full_context(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
static int xscale_restore_context(struct target *target)
{
static int xscale_restore_context(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
static int xscale_read_trace(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
static int xscale_read_trace(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
struct xscale_trace_data **trace_data_p;
/* 258 words from debug handler
struct xscale_trace_data **trace_data_p;
/* 258 words from debug handler
static void xscale_build_reg_cache(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
static void xscale_build_reg_cache(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
int i;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
int i;
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
uint32_t dcsr_value;
int retval;
uint32_t dcsr_value;
int retval;
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