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tcl/target/ti_k3: Set _CHIPNAME in one place
[openocd.git] / tcl / target / ti_k3.cfg
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 6c2c2e1dadafe553f60041c13941eac1423aa555..ffba478e76dd8ab70b0c358dc67c79a2bf0aea1c 100644 (file)
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -8,10 +8,18 @@
 #  Has 2 ARMV8 Cores and 6 R5 Cores and an M3
 # * J7200: https://www.ti.com/lit/pdf/spruiu1
 #  Has 2 ARMV8 Cores and 4 R5 Cores and an M3
+# * J721S2: https://www.ti.com/lit/pdf/spruj28
+#  Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
 # * AM642: https://www.ti.com/lit/pdf/spruim2
 #  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
+# * AM625: https://www.ti.com/lit/pdf/spruiv7a
+#  Has 4 ARMV8 Cores and 1 R5 Core and an M4F
+# * AM62a7: https://www.ti.com/lit/pdf/spruj16a
+#  Has 4 ARMV8 Cores and 2 R5 Cores
 #
 
+source [find target/swj-dp.tcl]
+
 if { [info exists SOC] } {
        set _soc $SOC
 } else {
@@ -55,7 +63,6 @@ set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
 # Set configuration overrides for each SOC
 switch $_soc {
        am654 {
-               set _CHIPNAME am654
                set _K3_DAP_TAPID 0x0bb5a02f
 
                # AM654 has 2 clusters of 2 A53 cores each.
@@ -64,16 +71,12 @@ switch $_soc {
 
                # AM654 has 1 cluster of 2 R5s cores.
                set _r5_cores 2
-               set _mcu_r5_cores 2
-               set _main0_r5_cores 0
-               set _main1_r5_cores 0
                set R5_NAMES {mcu_r5.0 mcu_r5.1}
 
                # Sysctrl power-ap unlock offsets
                set _sysctrl_ap_unlock_offsets {0xf0 0x50}
        }
        am642 {
-               set _CHIPNAME am642
                set _K3_DAP_TAPID 0x0bb3802f
 
                # AM642 has 1 clusters of 2 A53 cores each.
@@ -84,9 +87,6 @@ switch $_soc {
 
                # AM642 has 2 cluster of 2 R5s cores.
                set _r5_cores 4
-               set _mcu_r5_cores 0
-               set _main0_r5_cores 2
-               set _main1_r5_cores 2
                set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
                set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
                set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
@@ -94,8 +94,61 @@ switch $_soc {
                # M4 processor
                set _gp_mcu_cores 1
        }
+       am625 {
+               set _K3_DAP_TAPID 0x0bb7e02f
+
+               # AM625 has 1 clusters of 4 A53 cores.
+               set _armv8_cpu_name a53
+               set _armv8_cores 4
+               set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
+               set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
+
+               # AM625 has 1 cluster of 1 R5s core.
+               set _r5_cores 1
+               set R5_NAMES {main0_r5.0}
+               set R5_DBGBASE {0x9d410000}
+               set R5_CTIBASE {0x9d418000}
+
+               # sysctrl CTI base
+               set CM3_CTIBASE {0x20001000}
+               # Sysctrl power-ap unlock offsets
+               set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+               # M4 processor
+               set _gp_mcu_cores 1
+               set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+
+               # Setup DMEM access descriptions
+               # DAPBUS (Debugger) description
+               set _dmem_base_address 0x740002000
+               set _dmem_ap_address_offset 0x100
+               set _dmem_max_aps 10
+               # Emulated AP description
+               set _dmem_emu_base_address 0x760000000
+               set _dmem_emu_base_address_map_to 0x1d500000
+               set _dmem_emu_ap_list 1
+       }
+       am62a7 {
+               set _K3_DAP_TAPID 0x0bb8d02f
+
+               # AM62a7 has 1 clusters of 4 A53 cores.
+               set _armv8_cpu_name a53
+               set _armv8_cores 4
+               set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
+               set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
+
+               # AM62a7 has 2 cluster of 1 R5s core.
+               set _r5_cores 2
+               set R5_NAMES {main0_r5.0 mcu0_r5.0}
+               set R5_DBGBASE {0x9d410000 0x9d810000}
+               set R5_CTIBASE {0x9d418000 0x9d818000}
+
+               # sysctrl CTI base
+               set CM3_CTIBASE {0x20001000}
+               # Sysctrl power-ap unlock offsets
+               set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+       }
        j721e {
-               set _CHIPNAME j721e
                set _K3_DAP_TAPID 0x0bb6402f
                # J721E has 1 cluster of 2 A72 cores.
                set _armv8_cpu_name a72
@@ -103,12 +156,18 @@ switch $_soc {
 
                # J721E has 3 clusters of 2 R5 cores each.
                set _r5_cores 6
-               set _mcu_r5_cores 2
-               set _main0_r5_cores 2
-               set _main1_r5_cores 2
+
+               # Setup DMEM access descriptions
+               # DAPBUS (Debugger) description
+               set _dmem_base_address 0x4c40002000
+               set _dmem_ap_address_offset 0x100
+               set _dmem_max_aps 8
+               # Emulated AP description
+               set _dmem_emu_base_address 0x4c60000000
+               set _dmem_emu_base_address_map_to 0x1d600000
+               set _dmem_emu_ap_list 1
        }
        j7200 {
-               set _CHIPNAME j7200
                set _K3_DAP_TAPID 0x0bb6d02f
 
                # J7200 has 1 cluster of 2 A72 cores.
@@ -117,21 +176,40 @@ switch $_soc {
 
                # J7200 has 2 clusters of 2 R5 cores each.
                set _r5_cores 4
-               set _mcu_r5_cores 2
-               set _main0_r5_cores 2
-               set _main1_r5_cores 0
                set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
                set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
 
                # M3 CTI base
                set CM3_CTIBASE {0x20001000}
        }
+       j721s2 {
+               set _K3_DAP_TAPID 0x0bb7502f
+
+               # J721s2 has 1 cluster of 2 A72 cores.
+               set _armv8_cpu_name a72
+               set _armv8_cores 2
+
+               # J721s2 has 3 clusters of 2 R5 cores each.
+               set _r5_cores 6
+
+               # sysctrl CTI base
+               set CM3_CTIBASE {0x20001000}
+               # Sysctrl power-ap unlock offsets
+               set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+               # M4 processor
+               set _gp_mcu_cores 1
+               set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+       }
        default {
                echo "'$_soc' is invalid!"
        }
 }
 
-jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
+set _CHIPNAME $_soc
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
+
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
@@ -158,6 +236,24 @@ $_TARGETNAME.sysctrl configure -event gdb-attach {
        halt 1000
 }
 
+proc _cpu_no_smp_up {} {
+       set _current_target [target current]
+       set _current_type [$_current_target cget -type]
+
+       $_current_target arp_examine
+       $_current_target $_current_type dbginit
+}
+
+proc _armv8_smp_up {} {
+       for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
+               $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
+               $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+               $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
+       }
+       # Set Default target as core 0
+       targets $::_TARGETNAME.$::_armv8_cpu_name.0
+}
+
 set _v8_smp_targets ""
 
 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
@@ -169,6 +265,20 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
                -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
 
        set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
+
+       if { $_v8_smp_debug == 0 } {
+               $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+                       _cpu_no_smp_up
+                       # gdb-attach default rule
+                       halt 1000
+               }
+       } else {
+               $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+                       _armv8_smp_up
+                       # gdb-attach default rule
+                       halt 1000
+               }
+       }
 }
 
 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
@@ -178,22 +288,15 @@ set _armv8_smp_cmd "$_armv8_cpu_name"_smp
 
 if { $_v8_smp_debug == 0 } {
        proc $_armv8_up_cmd { args } {
-               foreach { _core } [set args] {
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+               foreach _core $args {
+                       targets $_core
+                       _cpu_no_smp_up
                }
        }
 } else {
        proc $_armv8_smp_cmd { args } {
-               for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
-               }
-               # Set Default target are core 0
-               targets $::_TARGETNAME.$::_armv8_cpu_name.0
+               _armv8_smp_up
        }
-
        # Declare SMP
        target smp $:::_v8_smp_targets
 }
@@ -206,32 +309,18 @@ for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
        # inactive core examination will fail - wait till startup of additional core
        target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
                -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
-}
-
-if { $_mcu_r5_cores != 0 } {
-       proc mcu_r5_up { args } {
-               foreach { _core } [set args] {
-                       $::_TARGETNAME.mcu_r5.$_core arp_examine
-                       $::_TARGETNAME.mcu_r5.$_core cortex_r4 dbginit
-               }
-       }
-}
 
-if { $_main0_r5_cores != 0 } {
-       proc main0_r5_up { args } {
-               foreach { _core } [set args] {
-                       $::_TARGETNAME.main0_r5.$_core arp_examine
-                       $::_TARGETNAME.main0_r5.$_core cortex_r4 dbginit
-               }
+       $_TARGETNAME.$_r5_name configure -event gdb-attach {
+               _cpu_no_smp_up
+               # gdb-attach default rule
+               halt 1000
        }
 }
 
-if { $_main1_r5_cores != 0 } {
-       proc main1_r5_up { args } {
-               foreach { _core } [set args] {
-                       $::_TARGETNAME.main1_r5.$_core arp_examine
-                       $::_TARGETNAME.main1_r5.$_core cortex_r4 dbginit
-               }
+proc r5_up { args } {
+       foreach  _core $args {
+               targets $_core
+               _cpu_no_smp_up
        }
 }
 
@@ -255,3 +344,22 @@ if { $_gp_mcu_cores != 0 } {
                halt 1000
        }
 }
+
+# In case of DMEM access, configure the dmem adapter with offsets from above.
+if { 0 == [string compare [adapter name] dmem ] } {
+       if { [info exists _dmem_base_address] } {
+               # DAPBUS (Debugger) description
+               dmem base_address $_dmem_base_address
+               dmem ap_address_offset $_dmem_ap_address_offset
+               dmem max_aps $_dmem_max_aps
+
+               # The following are the details of APs to be emulated for direct address access.
+               # Debug Config (Debugger) description
+               dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to
+               dmem emu_ap_list $_dmem_emu_ap_list
+               # We are going local bus, so speed is really dummy here.
+               adapter speed 2500
+       } else {
+               puts "ERROR: ${SOC} data is missing to support dmem access!"
+       }
+}
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