tcl/target/ti_k3: Add J784s4 SoC

[openocd.git] / tcl / target / ti_k3.cfg

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index ef1f1569a17e80f5eb2fd41b9a2bad6cadfe7419..beb98edca7e4d0e9137028727ccaa4cbb9372dbe 100644 (file)
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -10,6 +10,8 @@
 #  Has 2 ARMV8 Cores and 4 R5 Cores and an M3
 # * J721S2: https://www.ti.com/lit/pdf/spruj28
 #  Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
+# * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
+#  Has 8 ARMV8 Cores and 8 R5 Cores
 # * AM642: https://www.ti.com/lit/pdf/spruim2
 #  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
 # * AM625: https://www.ti.com/lit/pdf/spruiv7a
@@ -63,7 +65,6 @@ set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
 # Set configuration overrides for each SOC
 switch $_soc {
        am654 {
-               set _CHIPNAME am654
                set _K3_DAP_TAPID 0x0bb5a02f
 
                # AM654 has 2 clusters of 2 A53 cores each.
@@ -78,7 +79,6 @@ switch $_soc {
                set _sysctrl_ap_unlock_offsets {0xf0 0x50}
        }
        am642 {
-               set _CHIPNAME am642
                set _K3_DAP_TAPID 0x0bb3802f
 
                # AM642 has 1 clusters of 2 A53 cores each.
@@ -97,7 +97,6 @@ switch $_soc {
                set _gp_mcu_cores 1
        }
        am625 {
-               set _CHIPNAME am625
                set _K3_DAP_TAPID 0x0bb7e02f
 
                # AM625 has 1 clusters of 4 A53 cores.
@@ -132,7 +131,6 @@ switch $_soc {
                set _dmem_emu_ap_list 1
        }
        am62a7 {
-               set _CHIPNAME am62a7
                set _K3_DAP_TAPID 0x0bb8d02f
 
                # AM62a7 has 1 clusters of 4 A53 cores.
@@ -153,7 +151,6 @@ switch $_soc {
                set _sysctrl_ap_unlock_offsets {0xf0 0x78}
        }
        j721e {
-               set _CHIPNAME j721e
                set _K3_DAP_TAPID 0x0bb6402f
                # J721E has 1 cluster of 2 A72 cores.
                set _armv8_cpu_name a72
@@ -161,9 +158,18 @@ switch $_soc {
 
                # J721E has 3 clusters of 2 R5 cores each.
                set _r5_cores 6
+
+               # Setup DMEM access descriptions
+               # DAPBUS (Debugger) description
+               set _dmem_base_address 0x4c40002000
+               set _dmem_ap_address_offset 0x100
+               set _dmem_max_aps 8
+               # Emulated AP description
+               set _dmem_emu_base_address 0x4c60000000
+               set _dmem_emu_base_address_map_to 0x1d600000
+               set _dmem_emu_ap_list 1
        }
        j7200 {
-               set _CHIPNAME j7200
                set _K3_DAP_TAPID 0x0bb6d02f
 
                # J7200 has 1 cluster of 2 A72 cores.
@@ -179,7 +185,6 @@ switch $_soc {
                set CM3_CTIBASE {0x20001000}
        }
        j721s2 {
-               set _CHIPNAME j721s2
                set _K3_DAP_TAPID 0x0bb7502f
 
                # J721s2 has 1 cluster of 2 A72 cores.
@@ -198,11 +203,44 @@ switch $_soc {
                set _gp_mcu_cores 1
                set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
        }
+       j784s4 {
+               set _K3_DAP_TAPID 0x0bb8002f
+
+               # j784s4 has 2 cluster of 4 A72 cores each.
+               set _armv8_cpu_name a72
+               set _armv8_cores 8
+               set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000
+                           0x90810000 0x90910000 0x90a10000 0x90b10000}
+               set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000
+                           0x90820000 0x90920000 0x90a20000 0x90b20000}
+
+               # J721s2 has 4 clusters of 2 R5 cores each.
+               set _r5_cores 8
+               set R5_DBGBASE {0x9d010000 0x9d012000
+                        0x9d410000 0x9d412000
+                        0x9d510000 0x9d512000
+                        0x9d610000 0x9d612000}
+               set R5_CTIBASE {0x9d018000 0x9d019000
+                        0x9d418000 0x9d419000
+                        0x9d518000 0x9d519000
+                        0x9d618000 0x9d619000}
+               set R5_NAMES {mcu_r5.0 mcu_r5.1
+                      main0_r5.0 main0_r5.1
+                      main1_r5.0 main1_r5.1
+                      main2_r5.0 main2_r5.1}
+
+               # sysctrl CTI base
+               set CM3_CTIBASE {0x20001000}
+               # Sysctrl power-ap unlock offsets
+               set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+       }
        default {
                echo "'$_soc' is invalid!"
        }
 }
 
+set _CHIPNAME $_soc
+
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
 
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu