Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
tcl/target/ti_k3: Add AM273 SoC
[openocd.git] / tcl / target / ti_k3.cfg
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index ffba478e76dd8ab70b0c358dc67c79a2bf0aea1c..23825b86b43357effbcfc34fe9f9fbbf052117f3 100644 (file)
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -2,20 +2,30 @@
 # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
 #
 # Texas Instruments K3 devices:
+# * AM243: https://www.ti.com/lit/pdf/spruim2
+#  Has 4 R5 Cores, M4F and an M3
+# * AM263: https://www.ti.com/lit/pdf/spruj17
+#  Has 4 R5 Cores and an M3
+# * AM273: https://www.ti.com/lit/pdf/spruiu0
+#  Has 2 R5 Cores and an M3
+# * AM625: https://www.ti.com/lit/pdf/spruiv7a
+#  Has 4 ARMV8 Cores and 1 R5 Core and an M4F
+# * AM62A7: https://www.ti.com/lit/pdf/spruj16a
+#  Has 4 ARMV8 Cores and 2 R5 Cores
+# * AM62P: https://www.ti.com/lit/pdf/spruj83
+#  Has 4 ARMV8 Cores and 2 R5 Cores
+# * AM642: https://www.ti.com/lit/pdf/spruim2
+#  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
 # * AM654x: https://www.ti.com/lit/pdf/spruid7
 #  Has 4 ARMV8 Cores and 2 R5 Cores and an M3
-# * J721E: https://www.ti.com/lit/pdf/spruil1
-#  Has 2 ARMV8 Cores and 6 R5 Cores and an M3
 # * J7200: https://www.ti.com/lit/pdf/spruiu1
 #  Has 2 ARMV8 Cores and 4 R5 Cores and an M3
+# * J721E: https://www.ti.com/lit/pdf/spruil1
+#  Has 2 ARMV8 Cores and 6 R5 Cores and an M3
 # * J721S2: https://www.ti.com/lit/pdf/spruj28
 #  Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
-# * AM642: https://www.ti.com/lit/pdf/spruim2
-#  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
-# * AM625: https://www.ti.com/lit/pdf/spruiv7a
-#  Has 4 ARMV8 Cores and 1 R5 Core and an M4F
-# * AM62a7: https://www.ti.com/lit/pdf/spruj16a
-#  Has 4 ARMV8 Cores and 2 R5 Cores
+# * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
+#  Has 8 ARMV8 Cores and 8 R5 Cores
 #
 
 source [find target/swj-dp.tcl]
@@ -40,6 +50,7 @@ set CM3_CTIBASE               {0x3C016000}
 
 # sysctrl power-ap unlock offsets
 set _sysctrl_ap_unlock_offsets {0xf0 0x44}
+set _sysctrl_ap_num 7
 
 # All the ARMV8s are the next processors.
 #                 CL0,CORE0  CL0,CORE1  CL1,CORE0  CL1,CORE1
@@ -51,6 +62,7 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
 set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+set _r5_ap_num 1
 
 # Finally an General Purpose(GP) MCU
 set CM4_CTIBASE                {0x20001000}
@@ -60,8 +72,46 @@ set _gp_mcu_cores 0
 # General Purpose MCU power-ap unlock offsets
 set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
 
+# Generic mem-ap port number
+set _mem_ap_num 2
+
 # Set configuration overrides for each SOC
 switch $_soc {
+       am263 {
+               set _K3_DAP_TAPID 0x2bb7d02f
+
+               # Mem-ap port
+               set _mem_ap_num 6
+
+               # AM263 has 0 ARMV8 CPUs
+               set _armv8_cores 0
+
+               # AM263 has 2 cluster of 2 R5s cores.
+               set _r5_cores 4
+               set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+               set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000}
+               set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000}
+               set _r5_ap_num 5
+       }
+       am273 {
+               set _K3_DAP_TAPID 0x1bb6a02f
+
+               # Mem-ap port
+               set _mem_ap_num 6
+
+               # system controller is on AP0
+               set _sysctrl_ap_num 0
+
+               # AM273 has 0 ARMV8 CPUs
+               set _armv8_cores 0
+
+               # AM273 has 1 cluster of 2 R5s cores.
+               set _r5_cores 2
+               set R5_NAMES {main0_r5.0 main0_r5.1}
+               set R5_DBGBASE {0x90030000 0x90032000}
+               set R5_CTIBASE {0x90038000 0x90039000}
+               set _r5_ap_num 5
+       }
        am654 {
                set _K3_DAP_TAPID 0x0bb5a02f
 
@@ -76,6 +126,7 @@ switch $_soc {
                # Sysctrl power-ap unlock offsets
                set _sysctrl_ap_unlock_offsets {0xf0 0x50}
        }
+       am243 -
        am642 {
                set _K3_DAP_TAPID 0x0bb3802f
 
@@ -93,6 +144,12 @@ switch $_soc {
 
                # M4 processor
                set _gp_mcu_cores 1
+
+               # Overrides for am243
+               if { "$_soc" == "am243" } {
+                       # Uses the same JTAG ID
+                       set _armv8_cores 0
+               }
        }
        am625 {
                set _K3_DAP_TAPID 0x0bb7e02f
@@ -128,16 +185,17 @@ switch $_soc {
                set _dmem_emu_base_address_map_to 0x1d500000
                set _dmem_emu_ap_list 1
        }
+       am62p -
        am62a7 {
                set _K3_DAP_TAPID 0x0bb8d02f
 
-               # AM62a7 has 1 clusters of 4 A53 cores.
+               # AM62a7/AM62P has 1 cluster of 4 A53 cores.
                set _armv8_cpu_name a53
                set _armv8_cores 4
                set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
                set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
 
-               # AM62a7 has 2 cluster of 1 R5s core.
+               # AM62a7/AM62P has 2 cluster of 1 R5 core.
                set _r5_cores 2
                set R5_NAMES {main0_r5.0 mcu0_r5.0}
                set R5_DBGBASE {0x9d410000 0x9d810000}
@@ -147,6 +205,12 @@ switch $_soc {
                set CM3_CTIBASE {0x20001000}
                # Sysctrl power-ap unlock offsets
                set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+               # Overrides for am62p
+               if { "$_soc" == "am62p" } {
+                       set _K3_DAP_TAPID 0x0bb9d02f
+                       set R5_NAMES {wkup0_r5.0 mcu0_r5.0}
+               }
        }
        j721e {
                set _K3_DAP_TAPID 0x0bb6402f
@@ -201,11 +265,49 @@ switch $_soc {
                set _gp_mcu_cores 1
                set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
        }
+       j784s4 {
+               set _K3_DAP_TAPID 0x0bb8002f
+
+               # j784s4 has 2 cluster of 4 A72 cores each.
+               set _armv8_cpu_name a72
+               set _armv8_cores 8
+               set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000
+                           0x90810000 0x90910000 0x90a10000 0x90b10000}
+               set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000
+                           0x90820000 0x90920000 0x90a20000 0x90b20000}
+
+               # J721s2 has 4 clusters of 2 R5 cores each.
+               set _r5_cores 8
+               set R5_DBGBASE {0x9d010000 0x9d012000
+                        0x9d410000 0x9d412000
+                        0x9d510000 0x9d512000
+                        0x9d610000 0x9d612000}
+               set R5_CTIBASE {0x9d018000 0x9d019000
+                        0x9d418000 0x9d419000
+                        0x9d518000 0x9d519000
+                        0x9d618000 0x9d619000}
+               set R5_NAMES {mcu_r5.0 mcu_r5.1
+                      main0_r5.0 main0_r5.1
+                      main1_r5.0 main1_r5.1
+                      main2_r5.0 main2_r5.1}
+
+               # sysctrl CTI base
+               set CM3_CTIBASE {0x20001000}
+               # Sysctrl power-ap unlock offsets
+               set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+       }
        default {
                echo "'$_soc' is invalid!"
        }
 }
 
+proc _get_rtos_type_for_cpu { target_name } {
+       if { [info exists ::RTOS($target_name)] } {
+               return $::RTOS($target_name)
+       }
+       return none
+}
+
 set _CHIPNAME $_soc
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
@@ -217,8 +319,13 @@ set _TARGETNAME $_CHIPNAME.cpu
 set _CTINAME $_CHIPNAME.cti
 
 # sysctrl is always present
-cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
-target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
+cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \
+       -ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0]
+
+target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \
+       -ap-num $_sysctrl_ap_num -defer-examine \
+       -rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
+
 $_TARGETNAME.sysctrl configure -event reset-assert { }
 
 proc sysctrl_up {} {
@@ -261,8 +368,9 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
        cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
                -baseaddr [lindex $ARMV8_CTIBASE $_core]
 
-       target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \
-               -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
+       target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
+               -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
+               -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]
 
        set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
 
@@ -281,34 +389,37 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
        }
 }
 
-# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
-set _armv8_up_cmd "$_armv8_cpu_name"_up
-# Available if V8_SMP_DEBUG is set to non-zero value
-set _armv8_smp_cmd "$_armv8_cpu_name"_smp
+if { $_armv8_cores > 0 } {
+       # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
+       set _armv8_up_cmd "$_armv8_cpu_name"_up
+       # Available if V8_SMP_DEBUG is set to non-zero value
+       set _armv8_smp_cmd "$_armv8_cpu_name"_smp
 
-if { $_v8_smp_debug == 0 } {
-       proc $_armv8_up_cmd { args } {
-               foreach _core $args {
-                       targets $_core
-                       _cpu_no_smp_up
+       if { $_v8_smp_debug == 0 } {
+               proc $_armv8_up_cmd { args } {
+                       foreach _core $args {
+                               targets $_core
+                               _cpu_no_smp_up
+                       }
                }
+       } else {
+               proc $_armv8_smp_cmd { args } {
+                       _armv8_smp_up
+               }
+               # Declare SMP
+               target smp {*}$_v8_smp_targets
        }
-} else {
-       proc $_armv8_smp_cmd { args } {
-               _armv8_smp_up
-       }
-       # Declare SMP
-       target smp $:::_v8_smp_targets
 }
 
 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
        set _r5_name [lindex $R5_NAMES $_core]
-       cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
+       cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
                -baseaddr [lindex $R5_CTIBASE $_core]
 
        # inactive core examination will fail - wait till startup of additional core
        target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-               -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
+               -dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
+               -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
 
        $_TARGETNAME.$_r5_name configure -event gdb-attach {
                _cpu_no_smp_up
@@ -326,7 +437,8 @@ proc r5_up { args } {
 
 if { $_gp_mcu_cores != 0 } {
        cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
-       target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+       target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
+               -rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
        $_TARGETNAME.gp_mcu configure -event reset-assert { }
 
        proc gp_mcu_up {} {
@@ -362,4 +474,7 @@ if { 0 == [string compare [adapter name] dmem ] } {
        } else {
                puts "ERROR: ${SOC} data is missing to support dmem access!"
        }
+} else {
+       # AXI AP access port for SoC address map
+       target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num
 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)