target: add Espressif ESP32-S3 basic support

[openocd.git] / tcl / target / ti_cc3220sf.cfg

diff --git a/tcl/target/ti_cc3220sf.cfg b/tcl/target/ti_cc3220sf.cfg
index f7d9bfe17aab2aff1e67d2584d4b9f1dc3b74609..c0a7b568d3f739fd0d3e414c3cec74b73e94ad82 100644 (file)
--- a/tcl/target/ti_cc3220sf.cfg
+++ b/tcl/target/ti_cc3220sf.cfg
@@ -10,3 +10,31 @@ source [find target/ti_cc32xx.cfg]
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
+
+#
+# On CC32xx family of devices, sysreqreset is disabled, and vectreset is
+# blocked by the boot loader (stops in a while(1) statement). srst reset can
+# leave the target in a state that prevents debug. The following uses the
+# soft_reset_halt command to reset and halt the target. Then the PC and stack
+# are initialized from internal flash. This allows for a more reliable reset,
+# but with two caveats: it only works for the SF variant that has internal
+# flash, and it only resets the CPU and not any peripherals.
+#
+
+proc ocd_process_reset_inner { MODE } {
+
+       soft_reset_halt
+
+       # Initialize MSP, PSP, and PC from vector table at flash 0x01000800
+       set boot [read_memory 0x01000800 32 2]
+
+       reg msp [lindex $boot 0]
+       reg psp [lindex $boot 0]
+       reg pc [lindex $boot 1]
+
+       if { 0 == [string compare $MODE run ] } {
+               resume
+       }
+
+       cc32xx.cpu invoke-event reset-end
+}