tcl/cpld: add config files for more xilinx fpga families

[openocd.git] / tcl / target / stm32l1.cfg

diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg
index 7754c84939e4b898aa9b54fa8508b0a7686ab980..53d9076e19752626174605c306416a2c93a282e0 100644 (file)
--- a/tcl/target/stm32l1.cfg
+++ b/tcl/target/stm32l1.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # stm32l1 devices support both JTAG and SWD transports.
 #
@@ -23,9 +25,9 @@ if { [info exists WORKAREASIZE] } {
 
 # JTAG speed should be <= F_CPU/6.
 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
+adapter speed 300
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -45,33 +47,14 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID] } {
-   # FIXME this never gets used to override defaults...
-   set _BSTAPID $BSTAPID
-} else {
-   # See STM Document RM0038 Section 30.6.1 Rev. 12
-
-   # Low and medium density
-   set _BSTAPID1 0x06416041
-   # Cat.2 device (medium+ density)
-   set _BSTAPID2 0x06429041
-   # Cat.3 device (medium+ density)
-   set _BSTAPID3 0x06427041
-   # Cat.4 device, STM32L15/6xxD or Cat.3 device, some STM32L15/6xxC-A models
-   set _BSTAPID4 0x06436041
-   # Cat.5 device (high density), STM32L15/6xxE
-   set _BSTAPID5 0x06437041
-}
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
-   swj_newdap $_CHIPNAME bs -irlen 5 \
-   -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
-   -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
+   jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -92,13 +75,13 @@ proc stm32l_enable_HSI {} {
        echo "STM32L: Enabling HSI"
 
        # Set HSION in RCC_CR
-       mww 0x40023800 0x00000101
+       mmw 0x40023800 0x00000101 0
 
        # Set HSI as SYSCLK
-       mww 0x40023808 0x00000001
+       mmw 0x40023808 0x00000001 0
 
        # Increase JTAG speed
-       adapter_khz 2000
+       adapter speed 2000
 }
 
 $_TARGETNAME configure -event reset-init {
@@ -106,7 +89,7 @@ $_TARGETNAME configure -event reset-init {
 }
 
 $_TARGETNAME configure -event reset-start {
-       adapter_khz 300
+       adapter speed 300
 }
 
 $_TARGETNAME configure -event examine-end {
@@ -114,13 +97,20 @@ $_TARGETNAME configure -event examine-end {
        mmw 0xE0042004 0x00000007 0
 
        # Stop watchdog counters during halt
-       # DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
-       mww 0xE0042008 0x00001800
+       # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+       mmw 0xE0042008 0x00001800 0
 }
 
-$_TARGETNAME configure -event trace-config {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+       targets $_targetname
+
        # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
        # change this value accordingly to configure trace pins
        # assignment
        mmw 0xE0042004 0x00000020 0
 }
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"