psoc4: update for 4x00BLE, L, M, S and PRoC BLE devices

[openocd.git] / tcl / target / klx.cfg

diff --git a/tcl/target/klx.cfg b/tcl/target/klx.cfg
index c2de9f7d50b2a6270172dabfe1c67aba74d04718..1a2ee6798e13067d967611e5d64b46243cfe5de5 100644 (file)
--- a/tcl/target/klx.cfg
+++ b/tcl/target/klx.cfg
@@ -12,11 +12,11 @@ if { [info exists CHIPNAME] } {
 }
 
 # Work-area is a space in RAM used for flash programming
-# By default use 4kB
+# By default use 1KiB
 if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set _WORKAREASIZE 0x1000
+   set _WORKAREASIZE 0x400
 }
 
 if { [info exists CPUTAPID] } {
@@ -37,7 +37,8 @@ flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
 kinetis create_banks
 
 # Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
-# specifies up to 1MHz for VLPR mode.
+# specifies up to 1MHz for VLPR mode and up to 24MHz for run mode;
+# Table 17 of Sub-Family Data Sheet rev4 lists 25MHz as the maximum frequency.
 adapter_khz 1000
 
 reset_config srst_nogate
@@ -53,10 +54,9 @@ if {![using_hla]} {
    cortex_m reset_config sysresetreq
 }
 
-# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
-# specifies up to 24MHz for run mode; Table 17 of Sub-Family Data
-# Sheet rev4 lists 25MHz as the maximum frequency.
-# Uncoment only if VLPR mode is not used
-#$_TARGETNAME configure -event reset-init {
-#   adapter_khz 24000
-#}
+# Disable watchdog not to disturb OpenOCD algorithms running on MCU
+# (e.g. armv7m_checksum_memory() in verify_image)
+# Flash driver also disables watchdog before FTFA flash programming.
+$_TARGETNAME configure -event reset-init {
+   kinetis disable_wdog
+}