#ifndef XSCALE_H
#define XSCALE_H
-#include "armv4_5.h"
+#include "arm.h"
#include "armv4_5_mmu.h"
#include "trace.h"
#define XSCALE_LDIC 0x07
#define XSCALE_SELDCSR 0x09
+/* Possible CPU types */
+#define XSCALE_IXP4XX_PXA2XX 0x0
+#define XSCALE_PXA3XX 0x4
+
enum xscale_debug_reason
{
XSCALE_DBG_REASON_GENERIC,
uint32_t chkpt0;
uint32_t chkpt1;
uint32_t last_instruction;
+ unsigned int num_checkpoints;
struct xscale_trace_data *next;
};
+enum trace_mode
+{
+ XSCALE_TRACE_DISABLED,
+ XSCALE_TRACE_FILL,
+ XSCALE_TRACE_WRAP
+};
+
struct xscale_trace
{
- trace_status_t capture_status; /* current state of capture run */
struct image *image; /* source for target opcodes */
struct xscale_trace_data *data; /* linked list of collected trace data */
- int buffer_enabled; /* whether trace buffer is enabled */
- int buffer_fill; /* maximum number of trace runs to read (-1 for wrap-around) */
- int pc_ok;
- uint32_t current_pc;
- armv4_5_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */
+ int buffer_fill; /* maximum number of trace runs to read */
+ int fill_counter; /* running count during trace collection */
+ enum trace_mode mode;
+ enum arm_state core_state; /* current core state (ARM, Thumb) */
};
struct xscale_common
uint32_t cp15_control_reg;
int fast_memory_access;
+
+ /* CPU variant */
+ int xscale_variant;
};
static inline struct xscale_common *
XSCALE_TXRXCTRL,
};
-#define ERROR_XSCALE_NO_TRACE_DATA (-1500)
+#define ERROR_XSCALE_NO_TRACE_DATA (-700)
#endif /* XSCALE_H */