target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
- LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
+ LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
breakpoint->unique_id,
bp_num, comparator_list[bp_num].bp_value);
}
comparator_list[bp_num].used = 0;
comparator_list[bp_num].bp_value = 0;
target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
-
+
}
else
{
* and exclude both load and store accesses from watchpoint
* condition evaluation
*/
- int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
+ int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
(0xff << EJTAG_DBCn_BLM_SHIFT);
-
+
if (watchpoint->set)
{
LOG_WARNING("watchpoint already set");
target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
-
+
return ERROR_OK;
}
/* get pointers to arch-specific information */
mips32_common_t *mips32 = target->arch_info;
mips32_comparator_t * comparator_list = mips32->data_break_list;
-
+
if (!watchpoint->set)
{
LOG_WARNING("watchpoint not set");
LOG_INFO("no hardware watchpoints available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
-
+
mips32->num_data_bpoints_avail--;
mips_m4k_set_watchpoint(target, watchpoint);
if (ERROR_OK != retval)
return retval;
- /* TAP data register is loaded LSB first (little endian) */
- if (target->endianness == TARGET_BIG_ENDIAN)
- {
- uint32_t i, t32;
- uint16_t t16;
-
- for (i = 0; i < (count*size); i += size)
- {
- switch (size)
- {
- case 4:
- t32 = le_to_h_u32(&buffer[i]);
- h_u32_to_be(&buffer[i], t32);
- break;
- case 2:
- t16 = le_to_h_u16(&buffer[i]);
- h_u16_to_be(&buffer[i], t16);
- break;
- }
- }
- }
-
return ERROR_OK;
}
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
- /* TAP data register is loaded LSB first (little endian) */
- if (target->endianness == TARGET_BIG_ENDIAN)
- {
- uint32_t i, t32;
- uint16_t t16;
-
- for (i = 0; i < (count*size); i += size)
- {
- switch (size)
- {
- case 4:
- t32 = be_to_h_u32(&buffer[i]);
- h_u32_to_le(&buffer[i], t32);
- break;
- case 2:
- t16 = be_to_h_u16(&buffer[i]);
- h_u16_to_le(&buffer[i], t16);
- break;
- }
- }
- }
-
/* if noDMA off, use DMAACC mode for memory write */
if (ejtag_info->impcode & EJTAG_IMP_NODMA)
return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);