cfg: EFM32 supports SYSRESETREQ so use it

[openocd.git] / src / target / mips32_dmaacc.c

diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c
index 42979d71cc6aabb539a291ae007ea8b63ad66b7a..eb6cd8ce112791a7d4f68dfbf020713464ec8da6 100644 (file)
--- a/src/target/mips32_dmaacc.c
+++ b/src/target/mips32_dmaacc.c
@@ -20,7 +20,7 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -28,6 +28,7 @@
 #endif
 
 #include "mips32_dmaacc.h"
+#include <helper/time_support.h>
 
 static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info,
                uint32_t addr, int count, uint8_t *buf);
@@ -53,6 +54,22 @@ static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info,
  * displaying/modifying memory and memory mapped registers.
  */
 
+static int ejtag_dma_dstrt_poll(struct mips_ejtag *ejtag_info)
+{
+       uint32_t ejtag_ctrl;
+       int64_t start = timeval_ms();
+
+       do {
+               if (timeval_ms() - start > 1000) {
+                       LOG_ERROR("DMA time out");
+                       return -ETIMEDOUT;
+               }
+               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
+       return 0;
+}
+
 static int ejtag_dma_read(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *data)
 {
        uint32_t v;
@@ -72,10 +89,7 @@ begin_ejtag_dma_read:
        mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
        /* Wait for DSTRT to Clear */
-       do {
-               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
-               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-       } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
+       ejtag_dma_dstrt_poll(ejtag_info);
 
        /* Read Data */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
@@ -117,10 +131,7 @@ begin_ejtag_dma_read_h:
        mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
        /* Wait for DSTRT to Clear */
-       do {
-               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
-               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-       } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
+       ejtag_dma_dstrt_poll(ejtag_info);
 
        /* Read Data */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
@@ -167,10 +178,7 @@ begin_ejtag_dma_read_b:
        mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
        /* Wait for DSTRT to Clear */
-       do {
-               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
-               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-       } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
+       ejtag_dma_dstrt_poll(ejtag_info);
 
        /* Read Data */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
@@ -232,10 +240,7 @@ begin_ejtag_dma_write:
        mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
        /* Wait for DSTRT to Clear */
-       do {
-               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
-               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-       } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
+       ejtag_dma_dstrt_poll(ejtag_info);
 
        /* Clear DMA & Check DERR */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
@@ -281,10 +286,7 @@ begin_ejtag_dma_write_h:
        mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
        /* Wait for DSTRT to Clear */
-       do {
-               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
-               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-       } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
+       ejtag_dma_dstrt_poll(ejtag_info);
 
        /* Clear DMA & Check DERR */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
@@ -331,10 +333,7 @@ begin_ejtag_dma_write_b:
        mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
        /* Wait for DSTRT to Clear */
-       do {
-               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
-               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-       } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
+       ejtag_dma_dstrt_poll(ejtag_info);
 
        /* Clear DMA & Check DERR */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);