eol-style native

[openocd.git] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 7125e5af590f0009b1717b93ea7cde5b8305c399..a0832238c1a7313430781e94225793cde00b7819 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -225,6 +225,7 @@ int cortex_m3_endreset_event(target_t *target)
 
        /* Enable FPB */
        target_write_u32(target, FP_CTRL, 3);
+       cortex_m3->fpb_enabled = 1;
 
        /* Restore FPB registers */
        for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
@@ -739,7 +740,7 @@ int cortex_m3_assert_reset(target_t *target)
         * when srst is asserted the luminary device seesm to also clear the debug registers
         * which does not match the armv7 debug TRM */
                
-       if (strcmp(cortex_m3->variant, "lm3s") == 0)
+       if (strcmp(target->variant, "lm3s") == 0)
        {
                /* get revision of lm3s target, only early silicon has this issue
                 * Fury Rev B, DustDevil Rev B, Tempest all ok */
@@ -869,6 +870,11 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
                target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
                LOG_DEBUG("fpc_num %i fpcr_value 0x%x", fp_num, comparator_list[fp_num].fpcr_value);
+               if (!cortex_m3->fpb_enabled)
+               {
+                       LOG_DEBUG("FPB wasn't enabled, do it now");
+                       target_write_u32(target, FP_CTRL, 3);
+               }
        }
        else if (breakpoint->type == BKPT_SOFT)
        {
@@ -1401,10 +1407,11 @@ int cortex_m3_examine(struct target_s *target)
                /* Setup FPB */
                target_read_u32(target, FP_CTRL, &fpcr);
                cortex_m3->auto_bp_type = 1;
-               cortex_m3->fp_num_code = (fpcr >> 4) & 0xF;
+               cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
                cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
                cortex_m3->fp_code_available = cortex_m3->fp_num_code;
                cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t));
+               cortex_m3->fpb_enabled = fpcr & 1;
                for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
                {
                        cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
@@ -1510,7 +1517,7 @@ int cortex_m3_handle_target_request(void *priv)
        return ERROR_OK;
 }
 
-int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap, const char *variant)
+int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap)
 {
        armv7m_common_t *armv7m;
        armv7m = &cortex_m3->armv7m;
@@ -1538,15 +1545,6 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt
        armv7m->pre_restore_context = NULL;
        armv7m->post_restore_context = NULL;
        
-       if (variant)
-       {
-               cortex_m3->variant = strdup(variant);
-       }
-       else
-       {
-               cortex_m3->variant = strdup("");
-       }
-       
        armv7m_init_arch_info(target, armv7m);  
        armv7m->arch_info = cortex_m3;
        armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
@@ -1561,7 +1559,7 @@ int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
 {
        cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t));
        
-       cortex_m3_init_arch_info(target, cortex_m3, target->tap, target->variant);
+       cortex_m3_init_arch_info(target, cortex_m3, target->tap);
        
        return ERROR_OK;
 }