* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
+
#ifndef CORTEX_M3_H
#define CORTEX_M3_H
#include "armv7m.h"
-
#define CORTEX_M3_COMMON_MAGIC 0x1A451A45
#define SYSTEM_CONTROL_BASE 0x400FE000
+#define ITM_TER 0xE0000E00
+#define ITM_TPR 0xE0000E40
+#define ITM_TCR 0xE0000E80
+#define ITM_LAR 0xE0000FB0
+
#define CPUID 0xE000ED00
/* Debug Control Block */
#define DCB_DHCSR 0xE000EDF0
#define FP_COMP6 0xE0002020
#define FP_COMP7 0xE0002024
+#define FPU_CPACR 0xE000ED88
+#define FPU_FPCCR 0xE000EF34
+#define FPU_FPCAR 0xE000EF38
+#define FPU_FPDSCR 0xE000EF3C
+
+#define TPI_SSPSR 0xE0040000
+#define TPI_CSPSR 0xE0040004
+#define TPI_ACPR 0xE0040010
+#define TPI_SPPR 0xE00400F0
+#define TPI_FFSR 0xE0040300
+#define TPI_FFCR 0xE0040304
+#define TPI_FSCR 0xE0040308
+
/* DCB_DHCSR bit and field definitions */
#define DBGKEY (0xA05F << 16)
#define C_DEBUGEN (1 << 0)
#define S_RESET_ST (1 << 25)
/* DCB_DEMCR bit and field definitions */
-#define TRCENA (1 << 24)
-#define VC_HARDERR (1 << 10)
-#define VC_INTERR (1 << 9)
-#define VC_BUSERR (1 << 8)
-#define VC_STATERR (1 << 7)
-#define VC_CHKERR (1 << 6)
-#define VC_NOCPERR (1 << 5)
-#define VC_MMERR (1 << 4)
-#define VC_CORERESET (1 << 0)
+#define TRCENA (1 << 24)
+#define VC_HARDERR (1 << 10)
+#define VC_INTERR (1 << 9)
+#define VC_BUSERR (1 << 8)
+#define VC_STATERR (1 << 7)
+#define VC_CHKERR (1 << 6)
+#define VC_NOCPERR (1 << 5)
+#define VC_MMERR (1 << 4)
+#define VC_CORERESET (1 << 0)
#define NVIC_ICTR 0xE000E004
#define NVIC_ISE0 0xE000E100
#define FPCR_REPLACE_BKPT_HIGH (2 << 30)
#define FPCR_REPLACE_BKPT_BOTH (3 << 30)
-struct cortex_m3_fp_comparator
-{
+struct cortex_m3_fp_comparator {
int used;
int type;
uint32_t fpcr_value;
uint32_t fpcr_address;
};
-struct cortex_m3_dwt_comparator
-{
+struct cortex_m3_dwt_comparator {
int used;
uint32_t comp;
uint32_t mask;
uint32_t dwt_comparator_address;
};
-enum cortex_m3_soft_reset_config
-{
+enum cortex_m3_soft_reset_config {
CORTEX_M3_RESET_SYSRESETREQ,
CORTEX_M3_RESET_VECTRESET,
};
-enum cortex_m3_isrmasking_mode
-{
+enum cortex_m3_isrmasking_mode {
CORTEX_M3_ISRMASK_AUTO,
CORTEX_M3_ISRMASK_OFF,
CORTEX_M3_ISRMASK_ON,
};
-struct cortex_m3_common
-{
+struct cortex_m3_common {
int common_magic;
struct arm_jtag jtag_info;
struct cortex_m3_common, armv7m);
}
+int cortex_m3_examine(struct target *target);
int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
int cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint);
int cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
int cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
+void cortex_m3_enable_breakpoints(struct target *target);
void cortex_m3_enable_watchpoints(struct target *target);
void cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target);