cortex_m: handle armv8m cores without security extension

[openocd.git] / src / target / cortex_m.h

diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 168613590fb7c2e6eeeab547615414b56e675620..a1c43b56de526c164d02ae4afd9a43daad3fe24e 100644 (file)
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -36,6 +36,7 @@
 
 enum cortex_m_partno {
        CORTEX_M_PARTNO_INVALID,
+       STAR_MC1_PARTNO    = 0x132,
        CORTEX_M0_PARTNO   = 0xC20,
        CORTEX_M1_PARTNO   = 0xC21,
        CORTEX_M3_PARTNO   = 0xC23,
@@ -67,6 +68,9 @@ struct cortex_m_part_info {
 #define DCB_DEMCR      0xE000EDFC
 #define DCB_DSCSR      0xE000EE08
 
+#define DAUTHSTATUS    0xE000EFB8
+#define DAUTHSTATUS_SID_MASK   0x00000030
+
 #define DCRSR_WNR      BIT(16)
 
 #define DWT_CTRL       0xE0001000
@@ -206,6 +210,8 @@ struct cortex_m_common {
        /* Context information */
        uint32_t dcb_dhcsr;
        uint32_t dcb_dhcsr_cumulated_sticky;
+       /* DCB DHCSR has been at least once read, so the sticky bits have been reset */
+       bool dcb_dhcsr_sticky_is_recent;
        uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
        uint32_t nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */