armv7m_trace: get rid of the old tpiu code

[openocd.git] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 94cf824893e732edbc856f612b0fa4424c0ba8ad..b998b7ac76ae38f963c39593d56d3c4e7bb2a27f 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -39,6 +39,7 @@
 #include "arm_opcodes.h"
 #include "arm_semihosting.h"
 #include <helper/time_support.h>
+#include <rtt/rtt.h>
 
 /* NOTE:  most of this should work fine for the Cortex-M1 and
  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
@@ -1202,11 +1203,13 @@ static int cortex_m_assert_reset(struct target *target)
                if (retval3 != ERROR_OK)
                        LOG_DEBUG("Ignoring AP write error right after reset");
 
-               retval3 = dap_dp_init(armv7m->debug_ap->dap);
-               if (retval3 != ERROR_OK)
+               retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
+               if (retval3 != ERROR_OK) {
                        LOG_ERROR("DP initialisation failed");
-
-               else {
+                       /* The error return value must not be propagated in this case.
+                        * SYSRESETREQ or VECTRESET have been possibly triggered
+                        * so reset processing should continue */
+               } else {
                        /* I do not know why this is necessary, but it
                         * fixes strange effects (step/resume cause NMI
                         * after reset) on LM3S6918 -- Michael Schwingen
@@ -1249,7 +1252,8 @@ static int cortex_m_deassert_reset(struct target *target)
        if ((jtag_reset_config & RESET_HAS_SRST) &&
            !(jtag_reset_config & RESET_SRST_NO_GATING) &&
                target_was_examined(target)) {
-               int retval = dap_dp_init(armv7m->debug_ap->dap);
+
+               int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
                if (retval != ERROR_OK) {
                        LOG_ERROR("DP initialisation failed");
                        return retval;
@@ -2005,8 +2009,8 @@ int cortex_m_examine(struct target *target)
                }
                LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
 
-               /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
-               cortex_m->vectreset_supported = i > 1;
+               /* VECTRESET is supported only on ARMv7-M cores */
+               cortex_m->vectreset_supported = !armv7m->arm.is_armv8m && !armv7m->arm.is_armv6m;
 
                if (i == 4) {
                        target_read_u32(target, MVFR0, &mvfr0);
@@ -2076,10 +2080,8 @@ int cortex_m_examine(struct target *target)
                if (retval != ERROR_OK)
                        return retval;
 
-               if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
-                       armv7m_trace_tpiu_config(target);
+               if (armv7m->trace_config.itm_deferred_config)
                        armv7m_trace_itm_config(target);
-               }
 
                /* NOTE: FPB and DWT are both optional. */
 
@@ -2479,6 +2481,11 @@ static const struct command_registration cortex_m_command_handlers[] = {
        {
                .chain = armv7m_trace_command_handlers,
        },
+       /* START_DEPRECATED_TPIU */
+       {
+               .chain = arm_tpiu_deprecated_command_handlers,
+       },
+       /* END_DEPRECATED_TPIU */
        {
                .name = "cortex_m",
                .mode = COMMAND_EXEC,
@@ -2486,6 +2493,9 @@ static const struct command_registration cortex_m_command_handlers[] = {
                .usage = "",
                .chain = cortex_m_exec_command_handlers,
        },
+       {
+               .chain = rtt_target_command_handlers,
+       },
        COMMAND_REGISTRATION_DONE
 };