cortex_m: mark FPU register as non-existent instead of playing with num_regs

[openocd.git] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index ce2c426cee5bbdff91321b2af11500fd2922eee8..46b0e3c2a717a60bbb54fa3c4799df34f487cfd0 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -521,7 +521,7 @@ static int cortex_m_debug_entry(struct target *target)
 
        for (i = 0; i < num_regs; i++) {
                r = &armv7m->arm.core_cache->reg_list[i];
-               if (!r->valid)
+               if (r->exist && !r->valid)
                        arm->read_core_reg(target, r, i, ARM_MODE_ANY);
        }
 
@@ -1648,8 +1648,6 @@ void cortex_m_deinit_target(struct target *target)
 {
        struct cortex_m_common *cortex_m = target_to_cm(target);
 
-       armv7m_trace_tpiu_exit(target);
-
        free(cortex_m->fp_comparator_list);
 
        cortex_m_dwt_free(target);
@@ -2021,7 +2019,7 @@ int cortex_m_examine(struct target *target)
                        /* test for floating point feature on Cortex-M4 */
                        if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
                                LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
-                               armv7m->fp_feature = FPv4_SP;
+                               armv7m->fp_feature = FPV4_SP;
                        }
                } else if (i == 7 || i == 33 || i == 35 || i == 55) {
                        target_read_u32(target, MVFR0, &mvfr0);
@@ -2030,29 +2028,21 @@ int cortex_m_examine(struct target *target)
                        /* test for floating point features on Cortex-M7 */
                        if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
                                LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
-                               armv7m->fp_feature = FPv5_SP;
+                               armv7m->fp_feature = FPV5_SP;
                        } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
                                LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
-                               armv7m->fp_feature = FPv5_DP;
+                               armv7m->fp_feature = FPV5_DP;
                        }
                } else if (i == 0) {
                        /* Cortex-M0 does not support unaligned memory access */
                        armv7m->arm.is_armv6m = true;
                }
 
-               if (armv7m->fp_feature == FP_NONE &&
-                   armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
-                       /* free unavailable FPU registers */
-                       size_t idx;
+               /* Check for FPU, otherwise mark FPU register as non-existent */
+               if (armv7m->fp_feature == FP_NONE)
+                       for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
+                               armv7m->arm.core_cache->reg_list[idx].exist = false;
 
-                       for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
-                            idx < armv7m->arm.core_cache->num_regs;
-                            idx++) {
-                               free(armv7m->arm.core_cache->reg_list[idx].feature);
-                               free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
-                       }
-                       armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
-               }
 
                if (!armv7m->stlink) {
                        if (i == 3 || i == 4)
@@ -2082,10 +2072,8 @@ int cortex_m_examine(struct target *target)
                if (retval != ERROR_OK)
                        return retval;
 
-               if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
-                       armv7m_trace_tpiu_config(target);
+               if (armv7m->trace_config.itm_deferred_config)
                        armv7m_trace_itm_config(target);
-               }
 
                /* NOTE: FPB and DWT are both optional. */
 
@@ -2485,6 +2473,11 @@ static const struct command_registration cortex_m_command_handlers[] = {
        {
                .chain = armv7m_trace_command_handlers,
        },
+       /* START_DEPRECATED_TPIU */
+       {
+               .chain = arm_tpiu_deprecated_command_handlers,
+       },
+       /* END_DEPRECATED_TPIU */
        {
                .name = "cortex_m",
                .mode = COMMAND_EXEC,
@@ -2500,7 +2493,6 @@ static const struct command_registration cortex_m_command_handlers[] = {
 
 struct target_type cortexm_target = {
        .name = "cortex_m",
-       .deprecated_name = "cortex_m3",
 
        .poll = cortex_m_poll,
        .arch_state = armv7m_arch_state,