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- remove pipeline context, use once register instead - fix wrong register write in...
[openocd.git] / src / target / cortex_a8.c
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 76c3d37b18547350c69566db9b37ad61243a115c..f50b14955bd3550cd1f6b7cfdb97c58cb4e5a89a 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -73,7 +73,6 @@ static int cortex_a8_get_ttb(struct target *target, uint32_t *result);
  */
 #define swjdp_memoryap 0
 #define swjdp_debugap 1
-#define OMAP3530_DEBUG_BASE 0x54011000
 
 /*
  * Cortex-A8 Basic debug access, very low level assumes state is saved
@@ -300,7 +299,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
        if (dscr & DSCR_DTR_RX_FULL)
        {
                LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
-               /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
+               /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode  0xEE100E15 */
                retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
                                &dscr);
                if (retval != ERROR_OK)
@@ -319,7 +318,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
 
        if (Rd < 15)
        {
-               /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
+               /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
                retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
                                &dscr);
                if (retval != ERROR_OK)
@@ -327,7 +326,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
        }
        else if (Rd == 15)
        {
-               /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+               /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
                 * then "mov r15, r0"
                 */
                retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
@@ -340,7 +339,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
        }
        else
        {
-               /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+               /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
                 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
                 */
                retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
@@ -1056,12 +1055,16 @@ static int cortex_a8_debug_entry(struct target *target)
        /* Are we in an exception handler */
 //     armv4_5->exception_number = 0;
        if (armv7a->post_debug_entry)
-               armv7a->post_debug_entry(target);
+       {
+               retval = armv7a->post_debug_entry(target);
+               if (retval != ERROR_OK)
+                       return retval;
+       }
 
        return retval;
 }
 
-static void cortex_a8_post_debug_entry(struct target *target)
+static int cortex_a8_post_debug_entry(struct target *target)
 {
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
        struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
@@ -1072,6 +1075,8 @@ static void cortex_a8_post_debug_entry(struct target *target)
                        0, 0,   /* op1, op2 */
                        1, 0,   /* CRn, CRm */
                        &cortex_a8->cp15_control_reg);
+       if (retval != ERROR_OK)
+               return retval;
        LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
 
        if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
@@ -1083,6 +1088,8 @@ static void cortex_a8_post_debug_entry(struct target *target)
                                0, 1,   /* op1, op2 */
                                0, 0,   /* CRn, CRm */
                                &cache_type_reg);
+               if (retval != ERROR_OK)
+                       return retval;
                LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg);
 
                /* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
@@ -1097,7 +1104,7 @@ static void cortex_a8_post_debug_entry(struct target *target)
        armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
                        (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
 
-
+       return ERROR_OK;
 }
 
 static int cortex_a8_step(struct target *target, int current, uint32_t address,
@@ -1222,7 +1229,7 @@ static int cortex_a8_set_breakpoint(struct target *target,
                if (brp_i >= cortex_a8->brp_num)
                {
                        LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
-                       return ERROR_FAIL;
+                       return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
                }
                breakpoint->set = brp_i + 1;
                if (breakpoint->length == 2)
@@ -1352,9 +1359,8 @@ static int cortex_a8_add_breakpoint(struct target *target,
 
        if (breakpoint->type == BKPT_HARD)
                cortex_a8->brp_num_available--;
-       cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
 
-       return ERROR_OK;
+       return cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
 }
 
 static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
@@ -1707,12 +1713,7 @@ static int cortex_a8_examine_first(struct target *target)
        int i;
        int retval = ERROR_OK;
        uint32_t didr, ctypr, ttypr, cpuid;
-
-       /* stop assuming this is an OMAP! */
-       LOG_DEBUG("TODO - autoconfigure");
-
-       /* Here we shall insert a proper ROM Table scan */
-       armv7a->debug_base = OMAP3530_DEBUG_BASE;
+       uint32_t dbgbase, apid;
 
        /* We do one extra read to ensure DAP is configured,
         * we call ahbap_debugport_init(swjdp) instead
@@ -1721,6 +1722,17 @@ static int cortex_a8_examine_first(struct target *target)
        if (retval != ERROR_OK)
                return retval;
 
+       /* Get ROM Table base */
+       retval = dap_get_debugbase(swjdp, 1, &dbgbase, &apid);
+       if (retval != ERROR_OK)
+               return retval;
+
+       /* Lookup 0x15 -- Processor DAP */
+       retval = dap_lookup_cs_component(swjdp, 1, dbgbase, 0x15,
+                                       &armv7a->debug_base);
+       if (retval != ERROR_OK)
+               return retval;
+
        retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
        if (retval != ERROR_OK)
                return retval;
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