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Cache invalidation when writing to memory
[openocd.git] / src / target / cortex_a8.c
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 9585b35c2a658cb0de9980ce5b99b6ac854234c2..e73994e9c87ba36b76184f3874a0a546c7c39c5a 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -85,7 +85,6 @@ target_type_t cortexa8_target =
        .deassert_reset = NULL,
        .soft_reset_halt = NULL,
 
-//     .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
        .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 
        .read_memory = cortex_a8_read_memory,
@@ -166,7 +165,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
                retvalue = mem_ap_read_atomic_u32(swjdp,
                                OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
        }
-       while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+       while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
        mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
 
@@ -175,7 +174,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
                retvalue = mem_ap_read_atomic_u32(swjdp,
                                OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
        }
-       while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+       while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
        return retvalue;
 }
@@ -225,7 +224,6 @@ int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
 
 int cortex_a8_write_cp(target_t *target, uint32_t value,
        uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
-/* TODO Fix this */
 {
        int retval;
        /* get pointers to arch-specific information */
@@ -238,7 +236,7 @@ int cortex_a8_write_cp(target_t *target, uint32_t value,
        /* Move DTRRX to r0 */
        cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
 
-       cortex_a8_exec_opcode(target, ARMV4_5_MCR(CP, 0, 0, 0, 5, 0));
+       cortex_a8_exec_opcode(target, ARMV4_5_MCR(CP, op1, 0, CRn, CRm, op2));
        return retval;
 }
 
@@ -291,7 +289,7 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
                retval = mem_ap_read_atomic_u32(swjdp,
                                OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
        }
-       while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */
+       while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */
 
        retval = mem_ap_read_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
@@ -413,6 +411,8 @@ int cortex_a8_poll(target_t *target)
 int cortex_a8_halt(target_t *target)
 {
        int retval = ERROR_OK;
+       uint32_t dscr;
+
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv7a_common_t *armv7a = armv4_5->arch_info;
@@ -421,13 +421,32 @@ int cortex_a8_halt(target_t *target)
        uint8_t saved_apsel = dap_ap_get_select(swjdp);
        dap_ap_select(swjdp, swjdp_debugap);
 
-       /* Perhaps we should do a read-modify-write here */
+       /*
+        * Tell the core to be halted by writing DRCR with 0x1
+        * and then wait for the core to be halted.
+        */
        retval = mem_ap_write_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1);
 
+       /*
+        * enter halting debug mode
+        */
+       mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       retval = mem_ap_write_atomic_u32(swjdp,
+               OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
+
+       if (retval != ERROR_OK)
+               goto out;
+
+       do {
+               mem_ap_read_atomic_u32(swjdp,
+                       OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
+
        target->debug_reason = DBG_REASON_DBGRQ;
-       dap_ap_select(swjdp, saved_apsel);
 
+out:
+       dap_ap_select(swjdp, saved_apsel);
        return retval;
 }
 
@@ -437,11 +456,10 @@ int cortex_a8_resume(struct target_s *target, int current,
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv7a_common_t *armv7a = armv4_5->arch_info;
-       cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
        swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
 //     breakpoint_t *breakpoint = NULL;
-       uint32_t resume_pc;
+       uint32_t resume_pc, dscr;
 
        uint8_t saved_apsel = dap_ap_get_select(swjdp);
        dap_ap_select(swjdp, swjdp_debugap);
@@ -485,10 +503,17 @@ int cortex_a8_resume(struct target_s *target, int current,
        /* Make sure that the Armv7 gdb thumb fixups does not
         * kill the return address
         */
-       if (!(cortex_a8->cpudbg_dscr & (1 << 5)))
+       if (armv7a->core_state == ARMV7A_STATE_ARM)
        {
                resume_pc &= 0xFFFFFFFC;
        }
+       /* When the return address is loaded into PC
+        * bit 0 must be 1 to stay in Thumb state
+        */
+       if (armv7a->core_state == ARMV7A_STATE_THUMB)
+       {
+               resume_pc |= 0x1;
+       }
        LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
        buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).value,
@@ -515,10 +540,14 @@ int cortex_a8_resume(struct target_s *target, int current,
        }
 
 #endif
-       /* Restart core */
-       /* Perhaps we should do a read-modify-write here */
+       /* Restart core and wait for it to be started */
        mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x2);
 
+       do {
+               mem_ap_read_atomic_u32(swjdp,
+                       OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
+
        target->debug_reason = DBG_REASON_NOTHALTED;
        target->state = TARGET_RUNNING;
 
@@ -564,11 +593,10 @@ int cortex_a8_debug_entry(target_t *target)
        /* Enable the ITR execution once we are in debug mode */
        mem_ap_read_atomic_u32(swjdp,
                                OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
-       dscr |= (1 << 13);
+       dscr |= (1 << DSCR_EXT_INT_EN);
        retval = mem_ap_write_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
 
-
        /* Examine debug reason */
        switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
        {
@@ -589,7 +617,6 @@ int cortex_a8_debug_entry(target_t *target)
        }
 
        /* Examine target state and mode */
-       dap_ap_select(swjdp, swjdp_memoryap);
        if (cortex_a8->fast_reg_read)
                target_alloc_working_area(target, 64, &regfile_working_area);
 
@@ -602,6 +629,7 @@ int cortex_a8_debug_entry(target_t *target)
        }
        else
        {
+               dap_ap_select(swjdp, swjdp_memoryap);
                cortex_a8_read_regs_through_mem(target,
                                regfile_working_area->address, regfile);
                dap_ap_select(swjdp, swjdp_memoryap);
@@ -613,7 +641,8 @@ int cortex_a8_debug_entry(target_t *target)
        dap_ap_select(swjdp, swjdp_debugap);
        LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
-       armv4_5->core_mode = cpsr & 0x3F;
+       armv4_5->core_mode = cpsr & 0x1F;
+       armv7a->core_state = (cpsr & 0x20)?ARMV7A_STATE_THUMB:ARMV7A_STATE_ARM;
 
        for (i = 0; i <= ARM_PC; i++)
        {
@@ -632,8 +661,7 @@ int cortex_a8_debug_entry(target_t *target)
        ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
 
        /* Fixup PC Resume Address */
-       /* TODO Her we should use arch->core_state */
-       if (cortex_a8->cpudbg_dscr & (1 << 5))
+       if (armv7a->core_state == ARMV7A_STATE_THUMB)
        {
                // T bit set for Thumb or ThumbEE state
                regfile[ARM_PC] -= 4;
@@ -718,7 +746,6 @@ int cortex_a8_step(struct target_s *target, int current, uint32_t address,
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv7a_common_t *armv7a = armv4_5->arch_info;
-       cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
        breakpoint_t *breakpoint = NULL;
        breakpoint_t stepbreakpoint;
 
@@ -760,7 +787,7 @@ int cortex_a8_step(struct target_s *target, int current, uint32_t address,
 
        /* Setup single step breakpoint */
        stepbreakpoint.address = address;
-       stepbreakpoint.length = (cortex_a8->cpudbg_dscr & (1 << 5)) ? 2 : 4;
+       stepbreakpoint.length = (armv7a->core_state == ARMV7A_STATE_THUMB) ? 2 : 4;
        stepbreakpoint.type = BKPT_HARD;
        stepbreakpoint.set = 0;
 
@@ -1226,6 +1253,24 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
                        exit(-1);
        }
 
+       /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
+       /* invalidate I-Cache */
+       if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+       {
+               /* Invalidate ICache single entry with MVA, repeat this for all cache
+                  lines in the address range, Cortex-A8 has fixed 64 byte line length */
+               /* Invalidate Cache single entry with MVA to PoU */
+               for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
+                       armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */
+       }
+       /* invalidate D-Cache */
+       if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
+       {
+               /* Invalidate Cache single entry with MVA to PoC */
+               for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
+                       armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
+       }
+
        return retval;
 }
 
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