Mahr, Stefan <Stefan.Mahr@sphairon.com> removes the endianness swapping in mips_m4k...

[openocd.git] / src / target / cortex_a8.c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 9585b35c2a658cb0de9980ce5b99b6ac854234c2..6ef585cc7090c30c26f80eb4454ad9e9ae7e1d8d 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -166,7 +166,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
                retvalue = mem_ap_read_atomic_u32(swjdp,
                                OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
        }
-       while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+       while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
        mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
 
@@ -175,7 +175,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
                retvalue = mem_ap_read_atomic_u32(swjdp,
                                OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
        }
-       while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+       while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
        return retvalue;
 }
@@ -291,7 +291,7 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
                retval = mem_ap_read_atomic_u32(swjdp,
                                OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
        }
-       while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */
+       while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */
 
        retval = mem_ap_read_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
@@ -413,6 +413,8 @@ int cortex_a8_poll(target_t *target)
 int cortex_a8_halt(target_t *target)
 {
        int retval = ERROR_OK;
+       uint32_t dscr;
+
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv7a_common_t *armv7a = armv4_5->arch_info;
@@ -421,13 +423,32 @@ int cortex_a8_halt(target_t *target)
        uint8_t saved_apsel = dap_ap_get_select(swjdp);
        dap_ap_select(swjdp, swjdp_debugap);
 
-       /* Perhaps we should do a read-modify-write here */
+       /*
+        * Tell the core to be halted by writing DRCR with 0x1
+        * and then wait for the core to be halted.
+        */
        retval = mem_ap_write_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1);
 
+       /*
+        * enter halting debug mode
+        */
+       mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       retval = mem_ap_write_atomic_u32(swjdp,
+               OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
+
+       if (retval != ERROR_OK)
+               goto out;
+
+       do {
+               mem_ap_read_atomic_u32(swjdp,
+                       OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
+
        target->debug_reason = DBG_REASON_DBGRQ;
-       dap_ap_select(swjdp, saved_apsel);
 
+out:
+       dap_ap_select(swjdp, saved_apsel);
        return retval;
 }
 
@@ -441,7 +462,7 @@ int cortex_a8_resume(struct target_s *target, int current,
        swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
 //     breakpoint_t *breakpoint = NULL;
-       uint32_t resume_pc;
+       uint32_t resume_pc, dscr;
 
        uint8_t saved_apsel = dap_ap_get_select(swjdp);
        dap_ap_select(swjdp, swjdp_debugap);
@@ -515,10 +536,14 @@ int cortex_a8_resume(struct target_s *target, int current,
        }
 
 #endif
-       /* Restart core */
-       /* Perhaps we should do a read-modify-write here */
+       /* Restart core and wait for it to be started */
        mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x2);
 
+       do {
+               mem_ap_read_atomic_u32(swjdp,
+                       OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
+
        target->debug_reason = DBG_REASON_NOTHALTED;
        target->state = TARGET_RUNNING;
 
@@ -564,7 +589,7 @@ int cortex_a8_debug_entry(target_t *target)
        /* Enable the ITR execution once we are in debug mode */
        mem_ap_read_atomic_u32(swjdp,
                                OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
-       dscr |= (1 << 13);
+       dscr |= (1 << DSCR_EXT_INT_EN);
        retval = mem_ap_write_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
 
@@ -589,7 +614,6 @@ int cortex_a8_debug_entry(target_t *target)
        }
 
        /* Examine target state and mode */
-       dap_ap_select(swjdp, swjdp_memoryap);
        if (cortex_a8->fast_reg_read)
                target_alloc_working_area(target, 64, &regfile_working_area);
 
@@ -602,6 +626,7 @@ int cortex_a8_debug_entry(target_t *target)
        }
        else
        {
+               dap_ap_select(swjdp, swjdp_memoryap);
                cortex_a8_read_regs_through_mem(target,
                                regfile_working_area->address, regfile);
                dap_ap_select(swjdp, swjdp_memoryap);