.deassert_reset = NULL,
.soft_reset_halt = NULL,
-// .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.read_memory = cortex_a8_read_memory,
retval = mem_ap_write_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1);
+ /*
+ * enter halting debug mode
+ */
+ mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+ retval = mem_ap_write_atomic_u32(swjdp,
+ OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
+
if (retval != ERROR_OK)
goto out;
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
// breakpoint_t *breakpoint = NULL;
/* Make sure that the Armv7 gdb thumb fixups does not
* kill the return address
*/
- if (!(cortex_a8->cpudbg_dscr & (1 << 5)))
+ if (armv7a->core_state == ARMV7A_STATE_ARM)
{
resume_pc &= 0xFFFFFFFC;
}
+ /* When the return address is loaded into PC
+ * bit 0 must be 1 to stay in Thumb state
+ */
+ if (armv7a->core_state == ARMV7A_STATE_THUMB)
+ {
+ resume_pc |= 0x1;
+ }
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 15).value,
retval = mem_ap_write_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
-
/* Examine debug reason */
switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
{
dap_ap_select(swjdp, swjdp_debugap);
LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
- armv4_5->core_mode = cpsr & 0x3F;
+ armv4_5->core_mode = cpsr & 0x1F;
+ armv7a->core_state = (cpsr & 0x20)?ARMV7A_STATE_THUMB:ARMV7A_STATE_ARM;
for (i = 0; i <= ARM_PC; i++)
{
ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
/* Fixup PC Resume Address */
- /* TODO Her we should use arch->core_state */
- if (cortex_a8->cpudbg_dscr & (1 << 5))
+ if (armv7a->core_state == ARMV7A_STATE_THUMB)
{
// T bit set for Thumb or ThumbEE state
regfile[ARM_PC] -= 4;
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
breakpoint_t *breakpoint = NULL;
breakpoint_t stepbreakpoint;
/* Setup single step breakpoint */
stepbreakpoint.address = address;
- stepbreakpoint.length = (cortex_a8->cpudbg_dscr & (1 << 5)) ? 2 : 4;
+ stepbreakpoint.length = (armv7a->core_state == ARMV7A_STATE_THUMB) ? 2 : 4;
stepbreakpoint.type = BKPT_HARD;
stepbreakpoint.set = 0;