Alexei Babich <a.babich@rez.ru> cleanup

[openocd.git] / src / target / cortex_a8.c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 829bf3dca32f45f980281007c8ffd687847fe334..55a3c45b5549dbf61b3a2943f901b18257b95560 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -85,7 +85,6 @@ target_type_t cortexa8_target =
        .deassert_reset = NULL,
        .soft_reset_halt = NULL,
 
-//     .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
        .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 
        .read_memory = cortex_a8_read_memory,
@@ -166,7 +165,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
                retvalue = mem_ap_read_atomic_u32(swjdp,
                                OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
        }
-       while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+       while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
        mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
 
@@ -175,7 +174,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
                retvalue = mem_ap_read_atomic_u32(swjdp,
                                OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
        }
-       while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+       while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
        return retvalue;
 }
@@ -291,7 +290,7 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
                retval = mem_ap_read_atomic_u32(swjdp,
                                OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
        }
-       while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */
+       while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */
 
        retval = mem_ap_read_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
@@ -430,13 +429,20 @@ int cortex_a8_halt(target_t *target)
        retval = mem_ap_write_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1);
 
+       /*
+        * enter halting debug mode
+        */
+       mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       retval = mem_ap_write_atomic_u32(swjdp,
+               OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
+
        if (retval != ERROR_OK)
                goto out;
 
        do {
                mem_ap_read_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
-       } while ((dscr & (1 << 0)) == 0);
+       } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
 
        target->debug_reason = DBG_REASON_DBGRQ;
 
@@ -451,7 +457,6 @@ int cortex_a8_resume(struct target_s *target, int current,
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv7a_common_t *armv7a = armv4_5->arch_info;
-       cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
        swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
 //     breakpoint_t *breakpoint = NULL;
@@ -499,10 +504,17 @@ int cortex_a8_resume(struct target_s *target, int current,
        /* Make sure that the Armv7 gdb thumb fixups does not
         * kill the return address
         */
-       if (!(cortex_a8->cpudbg_dscr & (1 << 5)))
+       if (armv7a->core_state == ARMV7A_STATE_ARM)
        {
                resume_pc &= 0xFFFFFFFC;
        }
+       /* When the return address is loaded into PC
+        * bit 0 must be 1 to stay in Thumb state
+        */
+       if (armv7a->core_state == ARMV7A_STATE_THUMB)
+       {
+               resume_pc |= 0x1;
+       }
        LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
        buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).value,
@@ -535,7 +547,7 @@ int cortex_a8_resume(struct target_s *target, int current,
        do {
                mem_ap_read_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
-       } while ((dscr & (1 << 1)) == 0);
+       } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
 
        target->debug_reason = DBG_REASON_NOTHALTED;
        target->state = TARGET_RUNNING;
@@ -582,11 +594,10 @@ int cortex_a8_debug_entry(target_t *target)
        /* Enable the ITR execution once we are in debug mode */
        mem_ap_read_atomic_u32(swjdp,
                                OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
-       dscr |= (1 << 13);
+       dscr |= (1 << DSCR_EXT_INT_EN);
        retval = mem_ap_write_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
 
-
        /* Examine debug reason */
        switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
        {
@@ -631,7 +642,8 @@ int cortex_a8_debug_entry(target_t *target)
        dap_ap_select(swjdp, swjdp_debugap);
        LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
-       armv4_5->core_mode = cpsr & 0x3F;
+       armv4_5->core_mode = cpsr & 0x1F;
+       armv7a->core_state = (cpsr & 0x20)?ARMV7A_STATE_THUMB:ARMV7A_STATE_ARM;
 
        for (i = 0; i <= ARM_PC; i++)
        {
@@ -650,8 +662,7 @@ int cortex_a8_debug_entry(target_t *target)
        ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
 
        /* Fixup PC Resume Address */
-       /* TODO Her we should use arch->core_state */
-       if (cortex_a8->cpudbg_dscr & (1 << 5))
+       if (armv7a->core_state == ARMV7A_STATE_THUMB)
        {
                // T bit set for Thumb or ThumbEE state
                regfile[ARM_PC] -= 4;
@@ -736,7 +747,6 @@ int cortex_a8_step(struct target_s *target, int current, uint32_t address,
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv7a_common_t *armv7a = armv4_5->arch_info;
-       cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
        breakpoint_t *breakpoint = NULL;
        breakpoint_t stepbreakpoint;
 
@@ -778,7 +788,7 @@ int cortex_a8_step(struct target_s *target, int current, uint32_t address,
 
        /* Setup single step breakpoint */
        stepbreakpoint.address = address;
-       stepbreakpoint.length = (cortex_a8->cpudbg_dscr & (1 << 5)) ? 2 : 4;
+       stepbreakpoint.length = (armv7a->core_state == ARMV7A_STATE_THUMB) ? 2 : 4;
        stepbreakpoint.type = BKPT_HARD;
        stepbreakpoint.set = 0;