LOG_ERROR("How do I resume into Jazelle state??");
return ERROR_FAIL;
case ARM_STATE_AARCH64:
- LOG_ERROR("Shoudn't be in AARCH64 state");
+ LOG_ERROR("Shouldn't be in AARCH64 state");
return ERROR_FAIL;
}
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
static int cortex_a_deassert_reset(struct target *target)
{
+ struct armv7a_common *armv7a = target_to_armv7a(target);
int retval;
LOG_DEBUG(" ");
LOG_WARNING("%s: ran after reset and before halt ...",
target_name(target));
if (target_was_examined(target)) {
- retval = target_halt(target);
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
if (retval != ERROR_OK)
return retval;
} else
if (!count || !buffer)
return ERROR_COMMAND_SYNTAX_ERROR;
- LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+ LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
address, size, count);
/* read memory through the CPU */
int retval;
/* cortex_a handles unaligned memory access */
- LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+ LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
address, size, count);
cortex_a_prep_memaccess(target, 0);
if (!count || !buffer)
return ERROR_COMMAND_SYNTAX_ERROR;
- LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+ LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
address, size, count);
/* write memory through the CPU */
int retval;
/* cortex_a handles unaligned memory access */
- LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+ LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
address, size, count);
/* memory writes bypass the caches, must flush before writing */
target->coreid);
armv7a->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
}
+ if (dbg_idpfr1 & 0x0000f000) {
+ LOG_DEBUG("target->coreid %" PRId32 " has virtualization extensions",
+ target->coreid);
+ /*
+ * overwrite and simplify the checks.
+ * virtualization extensions require implementation of security extension
+ */
+ armv7a->arm.core_type = ARM_CORE_TYPE_VIRT_EXT;
+ }
/* Avoid recreating the registers cache */
if (!target_was_examined(target)) {
}
free(cortex_a->brp_list);
+ arm_free_reg_cache(dpm->arm);
free(dpm->dbp);
free(dpm->dwp);
free(target->private_config);