#define OPENOCD_TARGET_ARMV8_DPM_H
#include "arm_dpm.h"
+#include "helper/bits.h"
/* forward-declare struct armv8_common */
struct armv8_common;
int armv8_dpm_setup(struct arm_dpm *dpm);
int armv8_dpm_initialize(struct arm_dpm *dpm);
-int armv8_dpm_read_current_registers(struct arm_dpm *);
+int armv8_dpm_read_current_registers(struct arm_dpm *dpm);
int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
-int armv8_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
+int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp);
-void armv8_dpm_report_wfar(struct arm_dpm *, uint64_t wfar);
+void armv8_dpm_report_wfar(struct arm_dpm *dpm, uint64_t wfar);
/* DSCR bits; see ARMv7a arch spec section C10.3.1.
* Not all v7 bits are valid in v6.
#define DRCR_RESTART (1 << 1)
#define DRCR_CLEAR_EXCEPTIONS (1 << 2)
-/* PRCR (processor debug status register) bits */
+/* ECR (Execution Control Register) bits */
+#define ECR_RCE BIT(1)
+
+/* ESR (Event Status Register) bits */
+#define ESR_RC BIT(1)
+
+/* PRSR (processor debug status register) bits */
#define PRSR_PU (1 << 0)
#define PRSR_SPD (1 << 1)
#define PRSR_RESET (1 << 2)
#define PRSR_SPMAD (1 << 10)
#define PRSR_SDR (1 << 11)
+/* PRCR (processor debug control register) bits */
+#define PRCR_CORENPDRQ (1 << 0)
+#define PRCR_CWRR (1 << 2)
+#define PRCR_COREPURQ (1 << 3)
+
void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
+void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore);
enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm);
#endif /* OPENOCD_TARGET_ARM_DPM_H */