/* update dscr and el after each command execution */
dpm->dscr = dscr;
if (dpm->last_el != ((dscr >> 8) & 3))
- LOG_DEBUG("EL %i -> %i", dpm->last_el, (dscr >> 8) & 3);
+ LOG_DEBUG("EL %i -> %" PRIu32, dpm->last_el, (dscr >> 8) & 3);
dpm->last_el = (dscr >> 8) & 3;
if (dscr & DSCR_ERR) {
- LOG_ERROR("Opcode 0x%08"PRIx32", DSCR.ERR=1, DSCR.EL=%i", opcode, dpm->last_el);
+ LOG_ERROR("Opcode 0x%08" PRIx32 ", DSCR.ERR=1, DSCR.EL=%i", opcode, dpm->last_el);
armv8_dpm_handle_exception(dpm, true);
retval = ERROR_FAIL;
}
LOG_DEBUG("restoring mode, cpsr = 0x%08"PRIx32, cpsr);
} else {
- LOG_DEBUG("setting mode 0x%"PRIx32, mode);
+ LOG_DEBUG("setting mode 0x%x", mode);
cpsr = mode;
}
case ARM_MODE_ABT:
case ARM_MODE_IRQ:
case ARM_MODE_FIQ:
+ case ARM_MODE_SYS:
target_el = 1;
break;
/*
LOG_DEBUG("READ: %s, hvalue=%16.8llx", r->name, (unsigned long long) hvalue);
}
}
+
+ if (retval != ERROR_OK)
+ LOG_ERROR("Failed to read %s register", r->name);
+
return retval;
}
}
}
+ if (retval != ERROR_OK)
+ LOG_ERROR("Failed to write %s register", r->name);
+
return retval;
}
/**
- * Read basic registers of the the current context: R0 to R15, and CPSR;
+ * Read basic registers of the current context: R0 to R15, and CPSR;
* sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
* In normal operation this is called on entry to halting debug state,
* possibly after some other operations supporting restore of debug state
dpm->last_el != armv8_curel_from_core_mode(arm_reg->mode))
continue;
+ /* Special case: ARM_MODE_SYS has no SPSR at EL1 */
+ if (r->number == ARMV8_SPSR_EL1 && arm->core_mode == ARM_MODE_SYS)
+ continue;
+
retval = dpmv8_read_reg(dpm, r, i);
if (retval != ERROR_OK)
goto fail;
case DSCRV8_ENTRY_BKPT: /* SW BKPT (?) */
case DSCRV8_ENTRY_RESET_CATCH: /* Reset catch */
case DSCRV8_ENTRY_OS_UNLOCK: /*OS unlock catch*/
- case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/
case DSCRV8_ENTRY_SW_ACCESS_DBG: /*SW access dbg register*/
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case DSCRV8_ENTRY_WATCHPOINT: /* asynch watchpoint */
target->debug_reason = DBG_REASON_WATCHPOINT;
break;
+ case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/
+ target->debug_reason = DBG_REASON_EXC_CATCH;
+ break;
default:
target->debug_reason = DBG_REASON_UNDEFINED;
break;
/* FIXME add vector catch support */
dpm->nbp = 1 + ((dpm->didr >> 12) & 0xf);
- dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
+ dpm->dbp = calloc(dpm->nbp, sizeof(*dpm->dbp));
dpm->nwp = 1 + ((dpm->didr >> 20) & 0xf);
- dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
+ dpm->dwp = calloc(dpm->nwp, sizeof(*dpm->dwp));
if (!dpm->dbp || !dpm->dwp) {
free(dpm->dbp);