*/
static const struct {
unsigned id;
- char *name;
+ const char *name;
unsigned bits;
} armv7m_regs[] = {
{ ARMV7M_R0, "r0", 32 },
}
}
- if (armv7m->post_restore_context)
- armv7m->post_restore_context(target);
-
return ERROR_OK;
}
}
armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
- if (pc != exit_point)
+ if (exit_point && (pc != exit_point))
{
- LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
+ LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
return ERROR_TARGET_TIMEOUT;
}
return cache;
}
-int armv7m_setup_semihosting(struct target *target, int enable)
+static int armv7m_setup_semihosting(struct target *target, int enable)
{
/* nothing todo for armv7m */
return ERROR_OK;
struct reg_param reg_params[2];
int retval;
+ /* see contib/loaders/checksum/armv7m_crc.s for src */
+
static const uint16_t cortex_m3_crc_code[] = {
0x4602, /* mov r2, r0 */
0xF04F, 0x30FF, /* mov r0, #0xffffffff */
buf_set_u32(reg_params[0].value, 0, 32, address);
buf_set_u32(reg_params[1].value, 0, 32, count);
+ int timeout = 20000 * (1 + (count / (1024 * 1024)));
+
if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
- crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
+ crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), timeout, &armv7m_info)) != ERROR_OK)
{
LOG_ERROR("error executing cortex_m3 crc algorithm");
destroy_reg_param(®_params[0]);