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target/armv7m: rework Cortex-M register handling part 2
[openocd.git] / src / target / armv7m.c
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 3d73b295441c44890baeb5ea65e282c0b9a75d7c..177437391c3b698b339b6f0b8509c84ff7d5f81b 100644 (file)
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -48,7 +48,7 @@
 
 static const char * const armv7m_exception_strings[] = {
        "", "Reset", "NMI", "HardFault",
-       "MemManage", "BusFault", "UsageFault", "RESERVED",
+       "MemManage", "BusFault", "UsageFault", "SecureFault",
        "RESERVED", "RESERVED", "RESERVED", "SVCall",
        "DebugMonitor", "RESERVED", "PendSV", "SysTick"
 };
@@ -111,7 +111,7 @@ static const struct {
        { ARMV7M_PRIMASK, "primask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
        { ARMV7M_BASEPRI, "basepri", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
        { ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-       { ARMV7M_CONTROL, "control", 2, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+       { ARMV7M_CONTROL, "control", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
 
        { ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
        { ARMV7M_D1, "d1", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
@@ -191,7 +191,7 @@ static int armv7m_get_core_reg(struct reg *reg)
        if (target->state != TARGET_HALTED)
                return ERROR_TARGET_NOT_HALTED;
 
-       retval = arm->read_core_reg(target, reg, armv7m_reg->num, arm->core_mode);
+       retval = arm->read_core_reg(target, reg, reg->number, arm->core_mode);
 
        return retval;
 }
@@ -211,6 +211,40 @@ static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
        return ERROR_OK;
 }
 
+static uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
+{
+       switch (arm_reg_id) {
+       case ARMV7M_R0 ... ARMV7M_R14:
+       case ARMV7M_PC:
+       case ARMV7M_xPSR:
+       case ARMV7M_MSP:
+       case ARMV7M_PSP:
+               /* NOTE:  we "know" here that the register identifiers
+                * match the Cortex-M DCRSR.REGSEL selectors values
+                * for R0..R14, PC, xPSR, MSP, and PSP.
+                */
+               return arm_reg_id;
+
+       case ARMV7M_FPSCR:
+               return ARMV7M_REGSEL_FPSCR;
+
+       case ARMV7M_D0 ... ARMV7M_D15:
+               return ARMV7M_REGSEL_S0 + 2 * (arm_reg_id - ARMV7M_D0);
+
+       /* TODO: remove. This is temporary hack until packing/unpacking
+        * of special regs is moved to armv7m.c */
+       case ARMV7M_PRIMASK:
+       case ARMV7M_BASEPRI:
+       case ARMV7M_FAULTMASK:
+       case ARMV7M_CONTROL:
+               return arm_reg_id;
+
+       default:
+               LOG_ERROR("Bad register ID %u", arm_reg_id);
+               return arm_reg_id;
+       }
+}
+
 static int armv7m_read_core_reg(struct target *target, struct reg *r,
        int num, enum arm_mode mode)
 {
@@ -220,25 +254,27 @@ static int armv7m_read_core_reg(struct target *target, struct reg *r,
        struct armv7m_common *armv7m = target_to_armv7m(target);
 
        assert(num < (int)armv7m->arm.core_cache->num_regs);
+       assert(num == (int)r->number);
 
        armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
 
+       uint32_t regsel = armv7m_map_id_to_regsel(armv7m_core_reg->num);
+
        if ((armv7m_core_reg->num >= ARMV7M_D0) && (armv7m_core_reg->num <= ARMV7M_D15)) {
                /* map D0..D15 to S0..S31 */
-               size_t regidx = ARMV7M_S0 + 2 * (armv7m_core_reg->num - ARMV7M_D0);
-               retval = armv7m->load_core_reg_u32(target, regidx, &reg_value);
+               retval = armv7m->load_core_reg_u32(target, regsel, &reg_value);
                if (retval != ERROR_OK)
                        return retval;
                buf_set_u32(armv7m->arm.core_cache->reg_list[num].value,
                            0, 32, reg_value);
-               retval = armv7m->load_core_reg_u32(target, regidx + 1, &reg_value);
+               retval = armv7m->load_core_reg_u32(target, regsel + 1, &reg_value);
                if (retval != ERROR_OK)
                        return retval;
                buf_set_u32(armv7m->arm.core_cache->reg_list[num].value + 4,
                            0, 32, reg_value);
        } else {
                retval = armv7m->load_core_reg_u32(target,
-                                                  armv7m_core_reg->num, &reg_value);
+                                                  regsel, &reg_value);
                if (retval != ERROR_OK)
                        return retval;
                buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value);
@@ -258,27 +294,28 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r,
        struct armv7m_common *armv7m = target_to_armv7m(target);
 
        assert(num < (int)armv7m->arm.core_cache->num_regs);
+       assert(num == (int)r->number);
 
        armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
 
+       uint32_t regsel = armv7m_map_id_to_regsel(armv7m_core_reg->num);
+
        if ((armv7m_core_reg->num >= ARMV7M_D0) && (armv7m_core_reg->num <= ARMV7M_D15)) {
                /* map D0..D15 to S0..S31 */
-               size_t regidx = ARMV7M_S0 + 2 * (armv7m_core_reg->num - ARMV7M_D0);
-
                uint32_t t = buf_get_u32(value, 0, 32);
-               retval = armv7m->store_core_reg_u32(target, regidx, t);
+               retval = armv7m->store_core_reg_u32(target, regsel, t);
                if (retval != ERROR_OK)
                        goto out_error;
 
                t = buf_get_u32(value + 4, 0, 32);
-               retval = armv7m->store_core_reg_u32(target, regidx + 1, t);
+               retval = armv7m->store_core_reg_u32(target, regsel + 1, t);
                if (retval != ERROR_OK)
                        goto out_error;
        } else {
                uint32_t t = buf_get_u32(value, 0, 32);
 
                LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, t);
-               retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->num, t);
+               retval = armv7m->store_core_reg_u32(target, regsel, t);
                if (retval != ERROR_OK)
                        goto out_error;
        }
@@ -301,20 +338,22 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
                int *reg_list_size, enum target_register_class reg_class)
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
-       int i;
+       int i, size;
 
        if (reg_class == REG_CLASS_ALL)
-               *reg_list_size = armv7m->arm.core_cache->num_regs;
+               size = armv7m->arm.core_cache->num_regs;
        else
-               *reg_list_size = ARMV7M_NUM_CORE_REGS;
+               size = ARMV7M_NUM_CORE_REGS;
 
-       *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
+       *reg_list = malloc(sizeof(struct reg *) * size);
        if (*reg_list == NULL)
                return ERROR_FAIL;
 
-       for (i = 0; i < *reg_list_size; i++)
+       for (i = 0; i < size; i++)
                (*reg_list)[i] = &armv7m->arm.core_cache->reg_list[i];
 
+       *reg_list_size = size;
+
        return ERROR_OK;
 }
 
@@ -462,7 +501,6 @@ int armv7m_wait_algorithm(struct target *target,
        struct armv7m_common *armv7m = target_to_armv7m(target);
        struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
        int retval = ERROR_OK;
-       uint32_t pc;
 
        /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
         * at the exit point */
@@ -484,12 +522,14 @@ int armv7m_wait_algorithm(struct target *target,
                return ERROR_TARGET_TIMEOUT;
        }
 
-       armv7m->load_core_reg_u32(target, 15, &pc);
-       if (exit_point && (pc != exit_point)) {
-               LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
-                       pc,
-                       exit_point);
-               return ERROR_TARGET_TIMEOUT;
+       if (exit_point) {
+               /* PC value has been cached in cortex_m_debug_entry() */
+               uint32_t pc = buf_get_u32(armv7m->arm.pc->value, 0, 32);
+               if (pc != exit_point) {
+                       LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
+                                         pc, exit_point);
+                       return ERROR_TARGET_ALGO_EXIT;
+               }
        }
 
        /* Read memory values to mem_params[] */
@@ -695,7 +735,7 @@ int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
        /* Enable stimulus port #0 by default */
        armv7m->trace_config.itm_ter[0] = 1;
 
-       arm->core_type = ARM_MODE_THREAD;
+       arm->core_type = ARM_CORE_TYPE_M_PROFILE;
        arm->arch_info = armv7m;
        arm->setup_semihosting = armv7m_setup_semihosting;
 
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