.set = armv4_5_set_core_reg,
};
-struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
+struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
{
int num_regs = ARRAY_SIZE(arm_core_regs);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
{
/* Skip registers this core doesn't expose */
if (arm_core_regs[i].mode == ARM_MODE_MON
- && armv4_5_common->core_type != ARM_MODE_MON)
+ && arm->core_type != ARM_MODE_MON)
continue;
/* REVISIT handle Cortex-M, which only shadows R13/SP */
arch_info[i].num = arm_core_regs[i].cookie;
arch_info[i].mode = arm_core_regs[i].mode;
arch_info[i].target = target;
- arch_info[i].armv4_5_common = armv4_5_common;
+ arch_info[i].armv4_5_common = arm;
reg_list[i].name = (char *) arm_core_regs[i].name;
reg_list[i].size = 32;
cache->num_regs++;
}
- armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR;
- armv4_5_common->core_cache = cache;
+ arm->cpsr = reg_list + ARMV4_5_CPSR;
+ arm->core_cache = cache;
return cache;
}
{
struct arm *armv4_5 = target_to_arm(target);
- if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+ if (armv4_5->common_magic != ARM_COMMON_MAGIC)
{
LOG_ERROR("BUG: called for a non-ARM target");
return ERROR_FAIL;
int timeout_ms, void *arch_info))
{
struct arm *armv4_5 = target_to_arm(target);
- struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
+ struct arm_algorithm *arm_algorithm_info = arch_info;
enum arm_state core_state = armv4_5->core_state;
uint32_t context[17];
uint32_t cpsr;
LOG_DEBUG("Running algorithm");
- if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
+ if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC)
{
LOG_ERROR("current target isn't an ARMV4/5 target");
return ERROR_TARGET_INVALID;
struct reg *r;
r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5_algorithm_info->core_mode, i);
+ arm_algorithm_info->core_mode, i);
if (!r->valid)
armv4_5->read_core_reg(target, r, i,
- armv4_5_algorithm_info->core_mode);
+ arm_algorithm_info->core_mode);
context[i] = buf_get_u32(r->value, 0, 32);
}
cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
}
}
- armv4_5->core_state = armv4_5_algorithm_info->core_state;
+ armv4_5->core_state = arm_algorithm_info->core_state;
if (armv4_5->core_state == ARM_STATE_ARM)
exit_breakpoint_size = 4;
else if (armv4_5->core_state == ARM_STATE_THUMB)
return ERROR_INVALID_ARGUMENTS;
}
- if (armv4_5_algorithm_info->core_mode != ARM_MODE_ANY)
+ if (arm_algorithm_info->core_mode != ARM_MODE_ANY)
{
LOG_DEBUG("setting core_mode: 0x%2.2x",
- armv4_5_algorithm_info->core_mode);
+ arm_algorithm_info->core_mode);
buf_set_u32(armv4_5->cpsr->value, 0, 5,
- armv4_5_algorithm_info->core_mode);
+ arm_algorithm_info->core_mode);
armv4_5->cpsr->dirty = 1;
armv4_5->cpsr->valid = 1;
}
for (i = 0; i <= 16; i++)
{
uint32_t regvalue;
- regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
+ regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32);
if (regvalue != context[i])
{
- LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
+ LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).name, context[i]);
+ buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).valid = 1;
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).dirty = 1;
}
}
uint32_t address, uint32_t count, uint32_t *checksum)
{
struct working_area *crc_algorithm;
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
struct reg_param reg_params[2];
int retval;
uint32_t i;
return retval;
}
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
{
struct working_area *check_algorithm;
struct reg_param reg_params[3];
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
int retval;
uint32_t i;
return retval;
}
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
target->arch_info = armv4_5;
armv4_5->target = target;
- armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5->common_magic = ARM_COMMON_MAGIC;
arm_set_cpsr(armv4_5, ARM_MODE_USR);
/* core_type may be overridden by subtype logic */