target/aarch64: Add watchpoint support

[openocd.git] / src / target / arm_disassembler.h

diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index b73f24a8914cc23b87e6243358fe3b2945df0928..beecb3f30ffd8ef8fdd21becc59fdf827e75a479 100644 (file)
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -20,7 +20,7 @@
 #define OPENOCD_TARGET_ARM_DISASSEMBLER_H
 
 enum arm_instruction_type {
-       ARM_UNKNOWN_INSTUCTION,
+       ARM_UNKNOWN_INSTRUCTION,
 
        /* Branch instructions */
        ARM_B,
@@ -107,6 +107,7 @@ enum arm_instruction_type {
        ARM_MRRC,
        ARM_PLD,
        ARM_DSB,
+       ARM_ISB,
        ARM_QADD,
        ARM_QDADD,
        ARM_QSUB,
@@ -196,9 +197,11 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
                struct arm_instruction *instruction);
 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
                struct arm_instruction *instruction);
-int thumb2_opcode(struct target *target, uint32_t address,
-               struct arm_instruction *instruction);
 int arm_access_size(struct arm_instruction *instruction);
+#if HAVE_CAPSTONE
+int arm_disassemble(struct command_invocation *cmd, struct target *target,
+               target_addr_t address, size_t count, bool thumb_mode);
+#endif
 
 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])