typedef struct arm_b_bl_bx_blx_instr_s
{
int reg_operand;
- u32 target_address;
+ uint32_t target_address;
} arm_b_bl_bx_blx_instr_t;
union arm_shifter_operand
{
struct {
- u32 immediate;
+ uint32_t immediate;
} immediate;
struct {
- u8 Rm;
- u8 shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
- u8 shift_imm;
+ uint8_t Rm;
+ uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
+ uint8_t shift_imm;
} immediate_shift;
struct {
- u8 Rm;
- u8 shift;
- u8 Rs;
+ uint8_t Rm;
+ uint8_t shift;
+ uint8_t Rs;
} register_shift;
};
typedef struct arm_data_proc_instr_s
{
int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
- u8 S;
- u8 Rn;
- u8 Rd;
+ uint8_t S;
+ uint8_t Rn;
+ uint8_t Rd;
union arm_shifter_operand shifter_operand;
} arm_data_proc_instr_t;
typedef struct arm_load_store_instr_s
{
- u8 Rd;
- u8 Rn;
- u8 U;
+ uint8_t Rd;
+ uint8_t Rn;
+ uint8_t U;
int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
int offset_mode; /* 0: immediate, 1: (scaled) register */
union
{
- u32 offset;
+ uint32_t offset;
struct {
- u8 Rm;
- u8 shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
- u8 shift_imm;
+ uint8_t Rm;
+ uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
+ uint8_t shift_imm;
} reg;
} offset;
} arm_load_store_instr_t;
typedef struct arm_load_store_multiple_instr_s
{
- u8 Rn;
- u32 register_list;
- u8 addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
- u8 S;
- u8 W;
+ uint8_t Rn;
+ uint32_t register_list;
+ uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
+ uint8_t S;
+ uint8_t W;
} arm_load_store_multiple_instr_t;
typedef struct arm_instruction_s
{
enum arm_instruction_type type;
char text[128];
- u32 opcode;
+ uint32_t opcode;
union {
arm_b_bl_bx_blx_instr_t b_bl_bx_blx;
} arm_instruction_t;
-extern int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
-extern int thumb_evaluate_opcode(u16 opcode, u32 address, arm_instruction_t *instruction);
+extern int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *instruction);
+extern int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *instruction);
extern int arm_access_size(arm_instruction_t *instruction);
#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28])