#define DP_SELECT 0x8 /* JTAG: r/w; SWD: write */
#define DP_RDBUFF 0xC /* read-only */
+#define WCR_TO_TRN(wcr) (1 + (3 & ((wcr)) >> 8)) /* 1..4 clocks */
+#define WCR_TO_PRESCALE(wcr) (7 & ((wcr))) /* impl defined */
+
/* Fields of the DP's AP ABORT register */
#define DAPABORT (1 << 0)
#define STKCMPCLR (1 << 1) /* SWD-only */
/* Control config */
uint32_t dp_ctrl_stat;
+
+ uint32_t apsel;
+
/**
* Cache for DP_SELECT bits identifying the current AP. A DAP may
* connect to multiple APs, such as one MEM-AP for general access,
* another reserved for accessing debug modules, and a JTAG-DP.
* "-1" indicates no cached value.
*/
- uint32_t apsel;
+ uint32_t ap_current;
/**
* Cache for DP_SELECT bits identifying the current four-word AP
/** Accessor for currently selected DAP-AP number (0..255) */
static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
{
- return (uint8_t)(swjdp ->apsel >> 24);
+ return (uint8_t)(swjdp ->ap_current >> 24);
}
/* AP selection applies to future AP transactions */
-void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel);
+void dap_ap_select(struct adiv5_dap *dap,uint8_t ap);
/* Queued AP transactions */
int dap_setup_accessport(struct adiv5_dap *swjdp,
int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address);
+
+
+/* Queued MEM-AP memory mapped single word transfers with selection of ap */
+int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
+ uint32_t address, uint32_t *value);
+int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
+ uint32_t address, uint32_t value);
+
+/* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
+int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
+ uint32_t address, uint32_t *value);
+int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
+ uint32_t address, uint32_t value);
+
+/* MEM-AP memory mapped bus block transfers with selection of ap */
+int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
+ uint8_t *buffer, int count, uint32_t address);
+int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
+ uint8_t *buffer, int count, uint32_t address);
+int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
+ uint8_t *buffer, int count, uint32_t address);
+
+int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
+ uint8_t *buffer, int count, uint32_t address);
+int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
+ uint8_t *buffer, int count, uint32_t address);
+int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
+ uint8_t *buffer, int count, uint32_t address);
+
+
+
/* Initialisation of the debug system, power domains and registers */
int ahbap_debugport_init(struct adiv5_dap *swjdp);
/* Probe the AP for ROM Table location */
-int dap_get_debugbase(struct adiv5_dap *dap, int apsel,
+int dap_get_debugbase(struct adiv5_dap *dap, int ap,
uint32_t *dbgbase, uint32_t *apid);
+/* Lookup CoreSight component */
+int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
+ uint32_t dbgbase, uint8_t type, uint32_t *addr);
+
struct target;
/* Put debug link into SWD mode */