[0xF] = "CoreLink, PrimeCell or System component",
};
+#define ARCH_ID(architect, archid) ( \
+ (((architect) << ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \
+ (((archid) << ARM_CS_C9_DEVARCH_ARCHID_SHIFT) & ARM_CS_C9_DEVARCH_ARCHID_MASK) \
+)
+
+static const struct {
+ uint32_t arch_id;
+ const char *description;
+} class0x9_devarch[] = {
+ /* keep same unsorted order as in ARM IHI0029E */
+ { ARCH_ID(ARM_ID, 0x0A00), "RAS architecture" },
+ { ARCH_ID(ARM_ID, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" },
+ { ARCH_ID(ARM_ID, 0x1A02), "DWT architecture" },
+ { ARCH_ID(ARM_ID, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" },
+ { ARCH_ID(ARM_ID, 0x2A04), "Processor debug architecture (ARMv8-M)" },
+ { ARCH_ID(ARM_ID, 0x6A05), "Processor debug architecture (ARMv8-R)" },
+ { ARCH_ID(ARM_ID, 0x0A10), "PC sample-based profiling" },
+ { ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },
+ { ARCH_ID(ARM_ID, 0x1A14), "Cross Trigger Interface (CTI) architecture" },
+ { ARCH_ID(ARM_ID, 0x6A15), "Processor debug architecture (v8.0-A)" },
+ { ARCH_ID(ARM_ID, 0x7A15), "Processor debug architecture (v8.1-A)" },
+ { ARCH_ID(ARM_ID, 0x8A15), "Processor debug architecture (v8.2-A)" },
+ { ARCH_ID(ARM_ID, 0x2A16), "Processor Performance Monitor (PMU) architecture" },
+ { ARCH_ID(ARM_ID, 0x0A17), "Memory Access Port v2 architecture" },
+ { ARCH_ID(ARM_ID, 0x0A27), "JTAG Access Port v2 architecture" },
+ { ARCH_ID(ARM_ID, 0x0A31), "Basic trace router" },
+ { ARCH_ID(ARM_ID, 0x0A37), "Power requestor" },
+ { ARCH_ID(ARM_ID, 0x0A47), "Unknown Access Port v2 architecture" },
+ { ARCH_ID(ARM_ID, 0x0A50), "HSSTP architecture" },
+ { ARCH_ID(ARM_ID, 0x0A63), "System Trace Macrocell (STM) architecture" },
+ { ARCH_ID(ARM_ID, 0x0A75), "CoreSight ELA architecture" },
+ { ARCH_ID(ARM_ID, 0x0AF7), "CoreSight ROM architecture" },
+};
+
+#define DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
+
+__attribute__((unused))
+static const char *class0x9_devarch_description(uint32_t devarch)
+{
+ if (!(devarch & ARM_CS_C9_DEVARCH_PRESENT))
+ return "not present";
+
+ for (unsigned int i = 0; i < ARRAY_SIZE(class0x9_devarch); i++)
+ if ((devarch & DEVARCH_ID_MASK) == class0x9_devarch[i].arch_id)
+ return class0x9_devarch[i].description;
+
+ return "unknown";
+}
+
static const struct {
enum ap_type type;
const char *description;
* from chip observation (e.g. TI SDTI).
*/
-/* The legacy code only used the part number field to identify CoreSight peripherals.
- * This meant that the same part number from two different manufacturers looked the same.
- * It is desirable for all future additions to identify with both part number and JEP106.
- * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
- */
-
-#define ANY_ID 0x1000
-
static const struct dap_part_nums {
uint16_t designer_id;
uint16_t part_num;
{ ARM_ID, 0xd0c, "Neoverse N1", "(Debug Unit)", },
{ ARM_ID, 0xd13, "Cortex-R52 Debug", "(Debug Unit)", },
{ ARM_ID, 0xd49, "Neoverse N2", "(Debug Unit)", },
+ { 0x017, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
+ { 0x017, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
{ 0x017, 0x9af, "MSP432 ROM", "(ROM Table)" },
{ 0x01f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
{ 0x041, 0x1db, "XMC4500 ROM", "(ROM Table)" },
{ 0x1eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
{ 0x1eb, 0x302, "Denver Debug", "(Debug Unit)", },
{ 0x1eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
- /* legacy comment: 0x113: what? */
- { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
- { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
};
static const struct dap_part_nums *pidr_to_part_num(unsigned int designer_id, unsigned int part_num)
.full = "",
};
- for (unsigned int i = 0; i < ARRAY_SIZE(dap_part_nums); i++) {
- if (dap_part_nums[i].designer_id != designer_id && dap_part_nums[i].designer_id != ANY_ID)
- continue;
- if (dap_part_nums[i].part_num == part_num)
+ for (unsigned int i = 0; i < ARRAY_SIZE(dap_part_nums); i++)
+ if (dap_part_nums[i].designer_id == designer_id && dap_part_nums[i].part_num == part_num)
return &dap_part_nums[i];
- }
+
return &unknown;
}
command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid);
- const unsigned int class = (cid & ARM_CS_CIDR_CLASS_MASK) >> ARM_CS_CIDR_CLASS_SHIFT;
+ const unsigned int class = ARM_CS_CIDR_CLASS(cid);
const unsigned int part_num = ARM_CS_PIDR_PART(pid);
unsigned int designer_id = ARM_CS_PIDR_DESIGNER(pid);