Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
arm_adi_v5: describe Class 0x9 Device Architecture register
[openocd.git] / src / target / arm_adi_v5.c
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 469cb10ca4a05b8a65810b7fa468907d17c39553..d886a765f92420672cd5d7c547417715adc93ca5 100644 (file)
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -893,6 +893,55 @@ static const char *class_description[16] = {
        [0xF] = "CoreLink, PrimeCell or System component",
 };
 
+#define ARCH_ID(architect, archid) ( \
+       (((architect) << ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \
+       (((archid) << ARM_CS_C9_DEVARCH_ARCHID_SHIFT) & ARM_CS_C9_DEVARCH_ARCHID_MASK) \
+)
+
+static const struct {
+       uint32_t arch_id;
+       const char *description;
+} class0x9_devarch[] = {
+       /* keep same unsorted order as in ARM IHI0029E */
+       { ARCH_ID(ARM_ID, 0x0A00), "RAS architecture" },
+       { ARCH_ID(ARM_ID, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" },
+       { ARCH_ID(ARM_ID, 0x1A02), "DWT architecture" },
+       { ARCH_ID(ARM_ID, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" },
+       { ARCH_ID(ARM_ID, 0x2A04), "Processor debug architecture (ARMv8-M)" },
+       { ARCH_ID(ARM_ID, 0x6A05), "Processor debug architecture (ARMv8-R)" },
+       { ARCH_ID(ARM_ID, 0x0A10), "PC sample-based profiling" },
+       { ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },
+       { ARCH_ID(ARM_ID, 0x1A14), "Cross Trigger Interface (CTI) architecture" },
+       { ARCH_ID(ARM_ID, 0x6A15), "Processor debug architecture (v8.0-A)" },
+       { ARCH_ID(ARM_ID, 0x7A15), "Processor debug architecture (v8.1-A)" },
+       { ARCH_ID(ARM_ID, 0x8A15), "Processor debug architecture (v8.2-A)" },
+       { ARCH_ID(ARM_ID, 0x2A16), "Processor Performance Monitor (PMU) architecture" },
+       { ARCH_ID(ARM_ID, 0x0A17), "Memory Access Port v2 architecture" },
+       { ARCH_ID(ARM_ID, 0x0A27), "JTAG Access Port v2 architecture" },
+       { ARCH_ID(ARM_ID, 0x0A31), "Basic trace router" },
+       { ARCH_ID(ARM_ID, 0x0A37), "Power requestor" },
+       { ARCH_ID(ARM_ID, 0x0A47), "Unknown Access Port v2 architecture" },
+       { ARCH_ID(ARM_ID, 0x0A50), "HSSTP architecture" },
+       { ARCH_ID(ARM_ID, 0x0A63), "System Trace Macrocell (STM) architecture" },
+       { ARCH_ID(ARM_ID, 0x0A75), "CoreSight ELA architecture" },
+       { ARCH_ID(ARM_ID, 0x0AF7), "CoreSight ROM architecture" },
+};
+
+#define DEVARCH_ID_MASK         (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
+
+__attribute__((unused))
+static const char *class0x9_devarch_description(uint32_t devarch)
+{
+       if (!(devarch & ARM_CS_C9_DEVARCH_PRESENT))
+               return "not present";
+
+       for (unsigned int i = 0; i < ARRAY_SIZE(class0x9_devarch); i++)
+               if ((devarch & DEVARCH_ID_MASK) == class0x9_devarch[i].arch_id)
+                       return class0x9_devarch[i].description;
+
+       return "unknown";
+}
+
 static const struct {
        enum ap_type type;
        const char *description;
@@ -1107,20 +1156,12 @@ static int dap_read_part_id(struct adiv5_ap *ap, target_addr_t component_base, u
  * from chip observation (e.g. TI SDTI).
  */
 
-/* The legacy code only used the part number field to identify CoreSight peripherals.
- * This meant that the same part number from two different manufacturers looked the same.
- * It is desirable for all future additions to identify with both part number and JEP106.
- * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
- */
-
-#define ANY_ID 0x1000
-
-static const struct {
+static const struct dap_part_nums {
        uint16_t designer_id;
        uint16_t part_num;
        const char *type;
        const char *full;
-} dap_partnums[] = {
+} dap_part_nums[] = {
        { ARM_ID, 0x000, "Cortex-M3 SCS",              "(System Control Space)", },
        { ARM_ID, 0x001, "Cortex-M3 ITM",              "(Instrumentation Trace Module)", },
        { ARM_ID, 0x002, "Cortex-M3 DWT",              "(Data Watchpoint and Trace)", },
@@ -1131,9 +1172,12 @@ static const struct {
        { ARM_ID, 0x00c, "Cortex-M4 SCS",              "(System Control Space)", },
        { ARM_ID, 0x00d, "CoreSight ETM11",            "(Embedded Trace)", },
        { ARM_ID, 0x00e, "Cortex-M7 FPB",              "(Flash Patch and Breakpoint)", },
+       { ARM_ID, 0x193, "SoC-600 TSGEN",              "(Timestamp Generator)", },
        { ARM_ID, 0x470, "Cortex-M1 ROM",              "(ROM Table)", },
        { ARM_ID, 0x471, "Cortex-M0 ROM",              "(ROM Table)", },
        { ARM_ID, 0x490, "Cortex-A15 GIC",             "(Generic Interrupt Controller)", },
+       { ARM_ID, 0x492, "Cortex-R52 GICD",            "(Distributor)", },
+       { ARM_ID, 0x493, "Cortex-R52 GICR",            "(Redistributor)", },
        { ARM_ID, 0x4a1, "Cortex-A53 ROM",             "(v8 Memory Map ROM Table)", },
        { ARM_ID, 0x4a2, "Cortex-A57 ROM",             "(ROM Table)", },
        { ARM_ID, 0x4a3, "Cortex-A53 ROM",             "(v7 Memory Map ROM Table)", },
@@ -1142,6 +1186,7 @@ static const struct {
        { ARM_ID, 0x4aa, "Cortex-A35 ROM",             "(v8 Memory Map ROM Table)", },
        { ARM_ID, 0x4af, "Cortex-A15 ROM",             "(ROM Table)", },
        { ARM_ID, 0x4b5, "Cortex-R5 ROM",              "(ROM Table)", },
+       { ARM_ID, 0x4b8, "Cortex-R52 ROM",             "(ROM Table)", },
        { ARM_ID, 0x4c0, "Cortex-M0+ ROM",             "(ROM Table)", },
        { ARM_ID, 0x4c3, "Cortex-M3 ROM",              "(ROM Table)", },
        { ARM_ID, 0x4c4, "Cortex-M4 ROM",              "(ROM Table)", },
@@ -1187,11 +1232,25 @@ static const struct {
        { ARM_ID, 0x9a9, "Cortex-M7 TPIU",             "(Trace Port Interface Unit)", },
        { ARM_ID, 0x9ae, "Cortex-A17 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9af, "Cortex-A15 PMU",             "(Performance Monitor Unit)", },
+       { ARM_ID, 0x9b6, "Cortex-R52 PMU/CTI/ETM",     "(Performance Monitor Unit/Cross Trigger/ETM)", },
        { ARM_ID, 0x9b7, "Cortex-R7 PMU",              "(Performance Monitor Unit)", },
        { ARM_ID, 0x9d3, "Cortex-A53 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9d7, "Cortex-A57 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9d8, "Cortex-A72 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM",     "(Performance Monitor Unit/Cross Trigger/ETM)", },
+       { ARM_ID, 0x9e2, "SoC-600 APB-AP",             "(APB4 Memory Access Port)", },
+       { ARM_ID, 0x9e3, "SoC-600 AHB-AP",             "(AHB5 Memory Access Port)", },
+       { ARM_ID, 0x9e4, "SoC-600 AXI-AP",             "(AXI Memory Access Port)", },
+       { ARM_ID, 0x9e5, "SoC-600 APv1 Adapter",       "(Access Port v1 Adapter)", },
+       { ARM_ID, 0x9e6, "SoC-600 JTAG-AP",            "(JTAG Access Port)", },
+       { ARM_ID, 0x9e7, "SoC-600 TPIU",               "(Trace Port Interface Unit)", },
+       { ARM_ID, 0x9e8, "SoC-600 TMC ETR/ETS",        "(Embedded Trace Router/Streamer)", },
+       { ARM_ID, 0x9e9, "SoC-600 TMC ETB",            "(Embedded Trace Buffer)", },
+       { ARM_ID, 0x9ea, "SoC-600 TMC ETF",            "(Embedded Trace FIFO)", },
+       { ARM_ID, 0x9eb, "SoC-600 ATB Funnel",         "(Trace Funnel)", },
+       { ARM_ID, 0x9ec, "SoC-600 ATB Replicator",     "(Trace Replicator)", },
+       { ARM_ID, 0x9ed, "SoC-600 CTI",                "(Cross Trigger)", },
+       { ARM_ID, 0x9ee, "SoC-600 CATU",               "(Address Translation Unit)", },
        { ARM_ID, 0xc05, "Cortex-A5 Debug",            "(Debug Unit)", },
        { ARM_ID, 0xc07, "Cortex-A7 Debug",            "(Debug Unit)", },
        { ARM_ID, 0xc08, "Cortex-A8 Debug",            "(Debug Unit)", },
@@ -1206,6 +1265,11 @@ static const struct {
        { ARM_ID, 0xd07, "Cortex-A57 Debug",           "(Debug Unit)", },
        { ARM_ID, 0xd08, "Cortex-A72 Debug",           "(Debug Unit)", },
        { ARM_ID, 0xd0b, "Cortex-A76 Debug",           "(Debug Unit)", },
+       { ARM_ID, 0xd0c, "Neoverse N1",                "(Debug Unit)", },
+       { ARM_ID, 0xd13, "Cortex-R52 Debug",           "(Debug Unit)", },
+       { ARM_ID, 0xd49, "Neoverse N2",                "(Debug Unit)", },
+       { 0x017,  0x120, "TI SDTI",                    "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
+       { 0x017,  0x343, "TI DAPCTL",                  "", }, /* from OMAP3 memmap */
        { 0x017,  0x9af, "MSP432 ROM",                 "(ROM Table)" },
        { 0x01f,  0xcd0, "Atmel CPU with DSU",         "(CPU)" },
        { 0x041,  0x1db, "XMC4500 ROM",                "(ROM Table)" },
@@ -1222,11 +1286,166 @@ static const struct {
        { 0x1eb,  0x211, "Tegra 210 ROM",              "(ROM Table)", },
        { 0x1eb,  0x302, "Denver Debug",               "(Debug Unit)", },
        { 0x1eb,  0x402, "Denver PMU",                 "(Performance Monitor Unit)", },
-       /* legacy comment: 0x113: what? */
-       { ANY_ID, 0x120, "TI SDTI",                    "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
-       { ANY_ID, 0x343, "TI DAPCTL",                  "", }, /* from OMAP3 memmap */
 };
 
+static const struct dap_part_nums *pidr_to_part_num(unsigned int designer_id, unsigned int part_num)
+{
+       static const struct dap_part_nums unknown = {
+               .type = "Unrecognized",
+               .full = "",
+       };
+
+       for (unsigned int i = 0; i < ARRAY_SIZE(dap_part_nums); i++)
+               if (dap_part_nums[i].designer_id == designer_id && dap_part_nums[i].part_num == part_num)
+                       return &dap_part_nums[i];
+
+       return &unknown;
+}
+
+static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
+{
+       const char *major = "Reserved", *subtype = "Reserved";
+       const unsigned int minor = (devtype & ARM_CS_C9_DEVTYPE_SUB_MASK) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT;
+       const unsigned int devtype_major = (devtype & ARM_CS_C9_DEVTYPE_MAJOR_MASK) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT;
+       switch (devtype_major) {
+       case 0:
+               major = "Miscellaneous";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 4:
+                       subtype = "Validation component";
+                       break;
+               }
+               break;
+       case 1:
+               major = "Trace Sink";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 1:
+                       subtype = "Port";
+                       break;
+               case 2:
+                       subtype = "Buffer";
+                       break;
+               case 3:
+                       subtype = "Router";
+                       break;
+               }
+               break;
+       case 2:
+               major = "Trace Link";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 1:
+                       subtype = "Funnel, router";
+                       break;
+               case 2:
+                       subtype = "Filter";
+                       break;
+               case 3:
+                       subtype = "FIFO, buffer";
+                       break;
+               }
+               break;
+       case 3:
+               major = "Trace Source";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 1:
+                       subtype = "Processor";
+                       break;
+               case 2:
+                       subtype = "DSP";
+                       break;
+               case 3:
+                       subtype = "Engine/Coprocessor";
+                       break;
+               case 4:
+                       subtype = "Bus";
+                       break;
+               case 6:
+                       subtype = "Software";
+                       break;
+               }
+               break;
+       case 4:
+               major = "Debug Control";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 1:
+                       subtype = "Trigger Matrix";
+                       break;
+               case 2:
+                       subtype = "Debug Auth";
+                       break;
+               case 3:
+                       subtype = "Power Requestor";
+                       break;
+               }
+               break;
+       case 5:
+               major = "Debug Logic";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 1:
+                       subtype = "Processor";
+                       break;
+               case 2:
+                       subtype = "DSP";
+                       break;
+               case 3:
+                       subtype = "Engine/Coprocessor";
+                       break;
+               case 4:
+                       subtype = "Bus";
+                       break;
+               case 5:
+                       subtype = "Memory";
+                       break;
+               }
+               break;
+       case 6:
+               major = "Performance Monitor";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 1:
+                       subtype = "Processor";
+                       break;
+               case 2:
+                       subtype = "DSP";
+                       break;
+               case 3:
+                       subtype = "Engine/Coprocessor";
+                       break;
+               case 4:
+                       subtype = "Bus";
+                       break;
+               case 5:
+                       subtype = "Memory";
+                       break;
+               }
+               break;
+       }
+       command_print(cmd, "\t\tType is 0x%02x, %s, %s",
+                       devtype & ARM_CS_C9_DEVTYPE_MASK,
+                       major, subtype);
+       return ERROR_OK;
+}
+
 static int dap_rom_display(struct command_invocation *cmd,
                                struct adiv5_ap *ap, target_addr_t dbgbase, int depth)
 {
@@ -1264,41 +1483,24 @@ static int dap_rom_display(struct command_invocation *cmd,
 
        command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid);
 
-       uint8_t class = (cid & ARM_CS_CIDR_CLASS_MASK) >> ARM_CS_CIDR_CLASS_SHIFT;
-       uint16_t part_num = ARM_CS_PIDR_PART(pid);
-       uint16_t designer_id = ARM_CS_PIDR_DESIGNER(pid);
+       const unsigned int class = ARM_CS_CIDR_CLASS(cid);
+       const unsigned int part_num = ARM_CS_PIDR_PART(pid);
+       unsigned int designer_id = ARM_CS_PIDR_DESIGNER(pid);
 
        if (pid & ARM_CS_PIDR_JEDEC) {
                /* JEP106 code */
-               command_print(cmd, "\t\tDesigner is 0x%03" PRIx16 ", %s",
+               command_print(cmd, "\t\tDesigner is 0x%03x, %s",
                                designer_id, jep106_manufacturer(designer_id));
        } else {
                /* Legacy ASCII ID, clear invalid bits */
                designer_id &= 0x7f;
-               command_print(cmd, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
+               command_print(cmd, "\t\tDesigner ASCII code 0x%02x, %s",
                                designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
        }
 
-       /* default values to be overwritten upon finding a match */
-       const char *type = "Unrecognized";
-       const char *full = "";
-
-       /* search dap_partnums[] array for a match */
-       for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
-
-               if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
-                       continue;
-
-               if (dap_partnums[entry].part_num != part_num)
-                       continue;
-
-               type = dap_partnums[entry].type;
-               full = dap_partnums[entry].full;
-               break;
-       }
-
-       command_print(cmd, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
-       command_print(cmd, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
+       const struct dap_part_nums *partnum = pidr_to_part_num(designer_id, part_num);
+       command_print(cmd, "\t\tPart is 0x%03x, %s %s", part_num, partnum->type, partnum->full);
+       command_print(cmd, "\t\tComponent class is 0x%x, %s", class, class_description[class]);
 
        if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
                uint32_t memtype;
@@ -1333,150 +1535,15 @@ static int dap_rom_display(struct command_invocation *cmd,
                        }
                }
        } else if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
-               const char *major = "Reserved", *subtype = "Reserved";
-
                uint32_t devtype;
                retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C9_DEVTYPE, &devtype);
                if (retval != ERROR_OK)
                        return retval;
-               unsigned int minor = (devtype & ARM_CS_C9_DEVTYPE_SUB_MASK) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT;
-               unsigned int devtype_major = (devtype & ARM_CS_C9_DEVTYPE_MAJOR_MASK) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT;
-               switch (devtype_major) {
-               case 0:
-                       major = "Miscellaneous";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 4:
-                               subtype = "Validation component";
-                               break;
-                       }
-                       break;
-               case 1:
-                       major = "Trace Sink";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 1:
-                               subtype = "Port";
-                               break;
-                       case 2:
-                               subtype = "Buffer";
-                               break;
-                       case 3:
-                               subtype = "Router";
-                               break;
-                       }
-                       break;
-               case 2:
-                       major = "Trace Link";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 1:
-                               subtype = "Funnel, router";
-                               break;
-                       case 2:
-                               subtype = "Filter";
-                               break;
-                       case 3:
-                               subtype = "FIFO, buffer";
-                               break;
-                       }
-                       break;
-               case 3:
-                       major = "Trace Source";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 1:
-                               subtype = "Processor";
-                               break;
-                       case 2:
-                               subtype = "DSP";
-                               break;
-                       case 3:
-                               subtype = "Engine/Coprocessor";
-                               break;
-                       case 4:
-                               subtype = "Bus";
-                               break;
-                       case 6:
-                               subtype = "Software";
-                               break;
-                       }
-                       break;
-               case 4:
-                       major = "Debug Control";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 1:
-                               subtype = "Trigger Matrix";
-                               break;
-                       case 2:
-                               subtype = "Debug Auth";
-                               break;
-                       case 3:
-                               subtype = "Power Requestor";
-                               break;
-                       }
-                       break;
-               case 5:
-                       major = "Debug Logic";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 1:
-                               subtype = "Processor";
-                               break;
-                       case 2:
-                               subtype = "DSP";
-                               break;
-                       case 3:
-                               subtype = "Engine/Coprocessor";
-                               break;
-                       case 4:
-                               subtype = "Bus";
-                               break;
-                       case 5:
-                               subtype = "Memory";
-                               break;
-                       }
-                       break;
-               case 6:
-                       major = "Performance Monitor";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 1:
-                               subtype = "Processor";
-                               break;
-                       case 2:
-                               subtype = "DSP";
-                               break;
-                       case 3:
-                               subtype = "Engine/Coprocessor";
-                               break;
-                       case 4:
-                               subtype = "Bus";
-                               break;
-                       case 5:
-                               subtype = "Memory";
-                               break;
-                       }
-                       break;
-               }
-               command_print(cmd, "\t\tType is 0x%02x, %s, %s",
-                               devtype & ARM_CS_C9_DEVTYPE_MASK,
-                               major, subtype);
+
+               retval = dap_devtype_display(cmd, devtype);
+               if (retval != ERROR_OK)
+                       return retval;
+
                /* REVISIT also show ARM_CS_C9_DEVID */
        }
 
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)