/**
* flag to give info about cache manipulation during debug :
* "0" - cache lines are invalidated "on the fly", for affected addresses.
- * This is prefered from performance point of view.
+ * This is preferred from performance point of view.
* "1" - cache is invalidated and switched off on debug_entry, and switched back on on restore.
* It is kept off during debugging.
*/
return ERROR_OK;
}
+static void arm946e_deinit_target(struct target *target)
+{
+ struct arm *arm = target_to_arm(target);
+ struct arm946e_common *arm946e = target_to_arm946(target);
+
+ arm7_9_deinit(target);
+ arm_free_reg_cache(arm);
+ free(arm946e);
+}
+
static int arm946e_verify_pointer(struct command_invocation *cmd,
struct arm946e_common *arm946e)
{
*/
int nb_idx = (csize / (4*8*NB_CACHE_WAYS)); /* gives nb of lines (indexes) in the cache */
- /* Loop for all segmentde (i.e. ways) */
+ /* Loop for all segments (i.e. ways) */
uint32_t seg;
for (seg = 0; seg < NB_CACHE_WAYS; seg++) {
/* Loop for all indexes */
uint32_t value;
retval = arm946e_read_cp15(target, address, &value);
if (retval != ERROR_OK) {
- command_print(CMD, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+ command_print(CMD, "%s cp15 reg %" PRIu32 " access failed", target_name(target), address);
return retval;
}
retval = jtag_execute_queue();
retval = arm946e_write_cp15(target, address, value);
if (retval != ERROR_OK) {
- command_print(CMD, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+ command_print(CMD, "%s cp15 reg %" PRIu32 " access failed", target_name(target), address);
return retval;
}
if (address == CP15_CTL)
.commands = arm946e_command_handlers,
.target_create = arm946e_target_create,
.init_target = arm9tdmi_init_target,
+ .deinit_target = arm946e_deinit_target,
.examine = arm7_9_examine,
.check_reset = arm7_9_check_reset,
};