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- Fixes '<=' whitespace
[openocd.git] / src / target / arm7_9_common.c
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 909e108f594e904366ef1189c96ed0f8299ee8b3..985b9f63db84d2ca9e59e1c6ffd6336e163cd6fb 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -263,7 +263,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
        }
        else if (breakpoint->type == BKPT_SOFT)
        {
-               if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK)
+               if ((retval=arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
                        return retval;
 
                /* did we already set this breakpoint? */
@@ -290,7 +290,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                        }
                        if (verify != arm7_9->arm_bkpt)
                        {
-                               LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
+                               LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
                                return ERROR_OK;
                        }
                }
@@ -314,7 +314,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                        }
                        if (verify != arm7_9->thumb_bkpt)
                        {
-                               LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
+                               LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
                                return ERROR_OK;
                        }
                }
@@ -469,7 +469,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
-       if((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
+       if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
        {
                return retval;
        }
@@ -481,7 +481,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
        if (arm7_9->breakpoint_count==0)
        {
                /* make sure we don't have any dangling breakpoints */
-               if((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
+               if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
                {
                        return retval;
                }
@@ -526,12 +526,12 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
-               if( watchpoint->mask != 0xffffffffu )
+               if ( watchpoint->mask != 0xffffffffu )
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -543,12 +543,12 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
-               if( watchpoint->mask != 0xffffffffu )
+               if ( watchpoint->mask != 0xffffffffu )
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -593,7 +593,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
        if (watchpoint->set == 1)
        {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -602,7 +602,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
        else if (watchpoint->set == 2)
        {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -663,7 +663,7 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 
        if (watchpoint->set)
        {
-               if((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
+               if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
                {
                        return retval;
                }
@@ -711,7 +711,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
                if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
                                   && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
                        break;
-               if (debug_level>=3)
+               if (debug_level >= 3)
                {
                        alive_sleep(100);
                } else
@@ -721,7 +721,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
        }
        if (timeout)
        {
-               LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
+               LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
                return ERROR_TARGET_TIMEOUT;
        }
 
@@ -922,7 +922,7 @@ int arm7_9_poll(target_t *target)
                        {
                                reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
                                uint32_t t=*((uint32_t *)reg->value);
-                               if (t!=0)
+                               if (t != 0)
                                {
                                        LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
                                }
@@ -1022,7 +1022,7 @@ int arm7_9_assert_reset(target_t *target)
 
        armv4_5_invalidate_core_regs(target);
 
-       if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
+       if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
        {
                /* debug entry was already prepared in arm7_9_assert_reset() */
                target->debug_reason = DBG_REASON_DBGRQ;
@@ -1050,19 +1050,19 @@ int arm7_9_deassert_reset(target_t *target)
        jtag_add_reset(0, 0);
 
        enum reset_types jtag_reset_config = jtag_get_reset_config();
-       if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
+       if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
        {
                LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
                /* set up embedded ice registers again */
                if ((retval = target_examine_one(target)) != ERROR_OK)
                        return retval;
 
-               if ((retval=target_poll(target))!=ERROR_OK)
+               if ((retval=target_poll(target)) != ERROR_OK)
                {
                        return retval;
                }
 
-               if ((retval=target_halt(target))!=ERROR_OK)
+               if ((retval=target_halt(target)) != ERROR_OK)
                {
                        return retval;
                }
@@ -1147,7 +1147,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
        int i;
        int retval;
 
-       if ((retval=target_halt(target))!=ERROR_OK)
+       if ((retval=target_halt(target)) != ERROR_OK)
                return retval;
 
        long long then=timeval_ms();
@@ -1157,9 +1157,9 @@ int arm7_9_soft_reset_halt(struct target_s *target)
                if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
                        break;
                embeddedice_read_reg(dbg_stat);
-               if ((retval=jtag_execute_queue())!=ERROR_OK)
+               if ((retval=jtag_execute_queue()) != ERROR_OK)
                        return retval;
-               if (debug_level>=3)
+               if (debug_level >= 3)
                {
                        alive_sleep(100);
                } else
@@ -1363,7 +1363,7 @@ int arm7_9_debug_entry(target_t *target)
                /* Entered debug from Thumb mode */
                armv4_5->core_state = ARMV4_5_STATE_THUMB;
                arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
-               LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
+               LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32 ", pc_thumb: 0x%8.8" PRIx32 "", r0_thumb, pc_thumb);
        }
        else
        {
@@ -1428,15 +1428,15 @@ int arm7_9_debug_entry(target_t *target)
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
 
-       for (i=0; i<=15; i++)
+       for (i=0; i <= 15; i++)
        {
-               LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
+               LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
                buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
        }
 
-       LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
+       LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
 
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
@@ -1662,7 +1662,7 @@ int arm7_9_restore_context(target_t *target)
                                        num_regs++;
                                        reg->dirty = 0;
                                        reg->valid = 1;
-                                       LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
+                                       LOG_DEBUG("writing register %i of mode %s with value 0x%8.8" PRIx32 "", j, armv4_5_mode_strings[i], regs[j]);
                                }
                        }
 
@@ -1675,7 +1675,7 @@ int arm7_9_restore_context(target_t *target)
                        reg_arch_info = reg->arch_info;
                        if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
                        {
-                               LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
+                               LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
                                arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
                        }
                }
@@ -1689,20 +1689,20 @@ int arm7_9_restore_context(target_t *target)
                tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
                tmp_cpsr |= armv4_5_number_to_mode(i);
                tmp_cpsr &= ~0x20;
-               LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
+               LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
                arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
        }
        else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
        {
                /* CPSR has been changed, full restore necessary (mask T bit) */
-               LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+               LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
                arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
                armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
                armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
        }
 
        /* restore PC */
-       LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+       LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
        arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
        armv4_5->core_cache->reg_list[15].dirty = 0;
 
@@ -1807,7 +1807,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
        {
                if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
                {
-                       LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
+                       LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
                        if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
                        {
                                return retval;
@@ -1819,7 +1819,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
                        {
                                uint32_t current_opcode;
                                target_read_u32(target, current_pc, &current_opcode);
-                               LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
+                               LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
                                return retval;
                        }
 
@@ -1863,9 +1863,9 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
                        }
 
                        arm7_9_debug_entry(target);
-                       LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+                       LOG_DEBUG("new PC after step: 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 
-                       LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
+                       LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
                        if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
                        {
                                return retval;
@@ -1942,7 +1942,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
        uint32_t current_pc;
        current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
 
-       if(next_pc != current_pc)
+       if (next_pc != current_pc)
        {
                /* setup an inverse breakpoint on the current PC
                * - comparator 1 matches the current address
@@ -2024,7 +2024,7 @@ int arm7_9_step(struct target_s *target, int current, uint32_t address, int hand
        {
                uint32_t current_opcode;
                target_read_u32(target, current_pc, &current_opcode);
-               LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
+               LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
                return retval;
        }
 
@@ -2221,7 +2221,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
        int retval;
        int last_reg = 0;
 
-       LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
+       LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
 
        if (target->state != TARGET_HALTED)
        {
@@ -2297,7 +2297,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
                                                retval = arm7_9_execute_fast_sys_speed(target);
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
-                                       if(retval != ERROR_OK)
+                                       if (retval != ERROR_OK)
                                        {
                                                return retval;
                                        }
@@ -2335,7 +2335,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
                                                retval = arm7_9_execute_fast_sys_speed(target);
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
-                                       if(retval != ERROR_OK)
+                                       if (retval != ERROR_OK)
                                        {
                                                return retval;
                                        }
@@ -2362,7 +2362,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
 
-       for (i=0; i<=last_reg; i++)
+       for (i=0; i <= last_reg; i++)
                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
 
        arm7_9->read_xpsr(target, &cpsr, 0);
@@ -2374,7 +2374,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
 
        if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
        {
-               LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
+               LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
                arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 
@@ -2451,7 +2451,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
                                        retval = arm7_9_execute_fast_sys_speed(target);
                                else
                                        retval = arm7_9_execute_sys_speed(target);
-                               if(retval != ERROR_OK)
+                               if (retval != ERROR_OK)
                                {
                                        return retval;
                                }
@@ -2487,7 +2487,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
                                                retval = arm7_9_execute_fast_sys_speed(target);
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
-                                       if(retval != ERROR_OK)
+                                       if (retval != ERROR_OK)
                                        {
                                                return retval;
                                        }
@@ -2522,7 +2522,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
                                                retval = arm7_9_execute_fast_sys_speed(target);
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
-                                       if(retval != ERROR_OK)
+                                       if (retval != ERROR_OK)
                                        {
                                                return retval;
                                        }
@@ -2545,7 +2545,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
 
-       for (i=0; i<=last_reg; i++)
+       for (i=0; i <= last_reg; i++)
                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
 
        arm7_9->read_xpsr(target, &cpsr, 0);
@@ -2557,7 +2557,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
 
        if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
        {
-               LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
+               LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
                arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 
@@ -2576,7 +2576,7 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
-       if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK)
+       if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
                return retval;
 
        int little=target->endianness==TARGET_LITTLE_ENDIAN;
@@ -2587,7 +2587,7 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
                /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
                 * core function repeated. */
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
-               buffer+=4;
+               buffer += 4;
 
                embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
                uint8_t reg_addr = ice_reg->addr & 0x1f;
@@ -2608,7 +2608,7 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
                }
        }
 
-       if((retval = target_halt(target))!= ERROR_OK)
+       if ((retval = target_halt(target))!= ERROR_OK)
        {
                return retval;
        }
@@ -2677,9 +2677,9 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count,
        if (retval==ERROR_OK)
        {
                uint32_t endaddress=buf_get_u32(reg_params[0].value, 0, 32);
-               if (endaddress!=(address+count*4))
+               if (endaddress != (address+count*4))
                {
-                       LOG_ERROR("DCC write failed, expected end address 0x%08x got 0x%0x", (address+count*4), endaddress);
+                       LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address+count*4), endaddress);
                        retval=ERROR_FAIL;
                }
        }
@@ -2734,7 +2734,7 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c
        /* convert flash writing code into a buffer in target endianness */
        for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++)
        {
-               if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i]))!=ERROR_OK)
+               if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK)
                {
                        return retval;
                }
@@ -3087,7 +3087,7 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
 
        arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
 
-       if((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
+       if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
        {
                return retval;
        }
@@ -3120,12 +3120,12 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
        armv4_5->write_core_reg = arm7_9_write_core_reg;
        armv4_5->full_context = arm7_9_full_context;
 
-       if((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+       if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
        {
                return retval;
        }
 
-       if((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
+       if ((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
        {
                return retval;
        }
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