if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
&& (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
break;
- if (debug_level>=3)
+ if (debug_level >= 3)
{
alive_sleep(100);
} else
armv4_5_invalidate_core_regs(target);
- if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
+ if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
{
/* debug entry was already prepared in arm7_9_assert_reset() */
target->debug_reason = DBG_REASON_DBGRQ;
jtag_add_reset(0, 0);
enum reset_types jtag_reset_config = jtag_get_reset_config();
- if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
+ if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
{
LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
/* set up embedded ice registers again */
embeddedice_read_reg(dbg_stat);
if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
- if (debug_level>=3)
+ if (debug_level >= 3)
{
alive_sleep(100);
} else
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
return ERROR_FAIL;
- for (i=0; i<=15; i++)
+ for (i=0; i <= 15; i++)
{
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
return ERROR_FAIL;
- for (i=0; i<=last_reg; i++)
+ for (i=0; i <= last_reg; i++)
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
arm7_9->read_xpsr(target, &cpsr, 0);
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
return ERROR_FAIL;
- for (i=0; i<=last_reg; i++)
+ for (i=0; i <= last_reg; i++)
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
arm7_9->read_xpsr(target, &cpsr, 0);