ARM966 uses the new inheritance/nesting scheme

[openocd.git] / src / target / arm7_9_common.c

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 40dddda6c899fb0233b44267c523618f3a60aa12..21c5c7a2bb8bc51bafff8155b4289299785a1052 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1021,12 +1021,19 @@ int arm7_9_assert_reset(target_t *target)
                return ERROR_FAIL;
        }
 
-       /* at this point trst has been asserted/deasserted once. We want to
-        * program embedded ice while SRST is asserted, but some CPUs gate
-        * the JTAG clock while SRST is asserted
+       /* At this point trst has been asserted/deasserted once. We would
+        * like to program EmbeddedICE while SRST is asserted, instead of
+        * depending on SRST to leave that module alone.  However, many CPUs
+        * gate the JTAG clock while SRST is asserted; or JTAG may need
+        * clock stability guarantees (adaptive clocking might help).
+        *
+        * So we assume JTAG access during SRST is off the menu unless it's
+        * been specifically enabled.
         */
        bool srst_asserted = false;
-       if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) && ((jtag_reset_config & RESET_SRST_GATES_JTAG) == 0))
+
+       if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
+                       && (jtag_reset_config & RESET_SRST_NO_GATING))
        {
                jtag_add_reset(0, 1);
                srst_asserted = true;
@@ -1384,9 +1391,6 @@ int arm7_9_debug_entry(target_t *target)
        LOG_DEBUG("-");
 #endif
 
-       if (arm7_9->pre_debug_entry)
-               arm7_9->pre_debug_entry(target);
-
        /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
         * ensure that DBGRQ is cleared
         */
@@ -2814,8 +2818,11 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c
        buf_set_u32(reg_params[0].value, 0, 32, address);
        buf_set_u32(reg_params[1].value, 0, 32, count);
 
+       /* 20 second timeout/megabyte */
+       int timeout = 20000 * (1 + (count / (1024*1024)));
+
        if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
-               crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
+               crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), timeout, &armv4_5_info)) != ERROR_OK)
        {
                LOG_ERROR("error executing arm7_9 crc algorithm");
                destroy_reg_param(&reg_params[0]);
@@ -2952,8 +2959,8 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm
                return ERROR_OK;
        }
 
-       value = strtoul(args[0], NULL, 0);
-       spsr = strtol(args[1], NULL, 0);
+       COMMAND_PARSE_NUMBER(u32, args[0], value);
+       COMMAND_PARSE_NUMBER(int, args[1], spsr);
 
        /* if we're writing the CPSR, mask the T bit */
        if (!spsr)
@@ -2997,9 +3004,9 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char
                return ERROR_OK;
        }
 
-       value = strtoul(args[0], NULL, 0);
-       rotate = strtol(args[1], NULL, 0);
-       spsr = strtol(args[2], NULL, 0);
+       COMMAND_PARSE_NUMBER(u32, args[0], value);
+       COMMAND_PARSE_NUMBER(int, args[1], rotate);
+       COMMAND_PARSE_NUMBER(int, args[2], spsr);
 
        arm7_9->write_xpsr_im8(target, value, rotate, spsr);
        if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -3038,9 +3045,9 @@ int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char
                return ERROR_OK;
        }
 
-       num = strtol(args[0], NULL, 0);
-       mode = strtoul(args[1], NULL, 0);
-       value = strtoul(args[2], NULL, 0);
+       COMMAND_PARSE_NUMBER(int, args[0], num);
+       COMMAND_PARSE_NUMBER(u32, args[1], mode);
+       COMMAND_PARSE_NUMBER(u32, args[2], value);
 
        return arm7_9_write_core_reg(target, num, mode, value);
 }