* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
+ * Copyright (C) 2009 by Øyvind Harboe *
+ * oyvind.harboe@zylin.com *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
int arm720t_register_commands(struct command_context_s *cmd_ctx);
int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
/* forward declarations */
int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-int arm720t_quit(void);
int arm720t_arch_state(struct target_s *target);
int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm720t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm720t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm720t_soft_reset_halt(struct target_s *target);
+static int arm720t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
+static int arm720t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
+
target_type_t arm720t_target =
{
.name = "arm720t",
.read_memory = arm720t_read_memory,
.write_memory = arm720t_write_memory,
+ .read_phys_memory = arm720t_read_phys_memory,
+ .write_phys_memory = arm720t_write_phys_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory,
.target_create = arm720t_target_create,
.init_target = arm720t_init_target,
.examine = arm7tdmi_examine,
- .quit = arm720t_quit
+ .mrc = arm720t_mrc,
+ .mcr = arm720t_mcr,
+
};
int arm720t_scan_cp15(target_t *target, uint32_t out, uint32_t *in, int instruction, int clock)
buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
jtag_set_end_state(TAP_DRPAUSE);
- if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+ if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;
}
- if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
+ if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
{
return retval;
}
jtag_add_runtest(0, jtag_get_end_state());
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
- if((retval = jtag_execute_queue()) != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
else
LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
#else
- LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
+ LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
#endif
return ERROR_OK;
/* examine cp15 control reg */
arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
jtag_execute_queue();
- LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
+ LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
}
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
- "cpsr: 0x%8.8x pc: 0x%8.8x\n"
+ "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
- Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
+ Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
return retval;
}
+
+int arm720t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
+ arm720t_common_t *arm720t = arm7tdmi->arch_info;
+
+ return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
+}
+
+int arm720t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
+ arm720t_common_t *arm720t = arm7tdmi->arch_info;
+
+ return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
+}
+
+
int arm720t_soft_reset_halt(struct target_s *target)
{
int retval = ERROR_OK;
return retval;
}
- long long then=timeval_ms();
+ long long then = timeval_ms();
int timeout;
- while (!(timeout=((timeval_ms()-then)>1000)))
+ while (!(timeout = ((timeval_ms()-then) > 1000)))
{
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
{
break;
}
- if (debug_level>=3)
+ if (debug_level >= 3)
{
alive_sleep(100);
} else
return ERROR_OK;
}
-int arm720t_quit(void)
-{
- return ERROR_OK;
-}
int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap)
{
arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
- register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
-
- register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
- register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
- register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
-
- register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
- register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
- register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
return ERROR_OK;
}
/* one or more argument, access a single register (write if second argument is given */
if (argc >= 1)
{
- uint32_t opcode = strtoul(args[0], NULL, 0);
+ uint32_t opcode;
+ COMMAND_PARSE_NUMBER(u32, args[0], opcode);
if (argc == 1)
{
uint32_t value;
if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
{
- command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
+ command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
return ERROR_OK;
}
return retval;
}
- command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
+ command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
}
else if (argc == 2)
{
- uint32_t value = strtoul(args[1], NULL, 0);
+ uint32_t value;
+ COMMAND_PARSE_NUMBER(u32, args[1], value);
+
if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
{
- command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
+ command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
return ERROR_OK;
}
- command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
+ command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
}
}
return ERROR_OK;
}
-int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm7tdmi_common_t *arm7tdmi;
- arm720t_common_t *arm720t;
- arm_jtag_t *jtag_info;
-
- if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM720t target");
- return ERROR_OK;
- }
-
- jtag_info = &arm7_9->jtag_info;
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
-
- return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
-}
-
-int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+static int arm720t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm7tdmi_common_t *arm7tdmi;
- arm720t_common_t *arm720t;
- arm_jtag_t *jtag_info;
-
- if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
+ if (cpnum!=15)
{
- command_print(cmd_ctx, "current target isn't an ARM720t target");
- return ERROR_OK;
+ LOG_ERROR("Only cp15 is supported");
+ return ERROR_FAIL;
}
- jtag_info = &arm7_9->jtag_info;
+ return arm720t_read_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
-
- return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
}
-int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+static int arm720t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm7tdmi_common_t *arm7tdmi;
- arm720t_common_t *arm720t;
- arm_jtag_t *jtag_info;
-
- if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
+ if (cpnum!=15)
{
- command_print(cmd_ctx, "current target isn't an ARM720t target");
- return ERROR_OK;
+ LOG_ERROR("Only cp15 is supported");
+ return ERROR_FAIL;
}
- jtag_info = &arm7_9->jtag_info;
+ return arm720t_write_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
+}
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
- return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
-}
Code Review / openocd.git / blobdiff