#define ARM11_H
#include "armv4_5.h"
+#include "arm_dpm.h"
-#define asizeof(x) (sizeof(x) / sizeof((x)[0]))
-
-#define NEW(type, variable, items) \
- type * variable = calloc(1, sizeof(type) * items)
-
-/* For MinGW use 'I' prefix to print size_t (instead of 'z') */
-/* Except if __USE_MINGW_ANSI_STDIO is defined with MinGW */
-
-#if (!defined(__MSVCRT__) || defined(__USE_MINGW_ANSI_STDIO))
-#define ZU "%zu"
-#else
-#define ZU "%Iu"
-#endif
-
-#define ARM11_REGCACHE_MODEREGS 0
-#define ARM11_REGCACHE_FREGS 0
-
-#define ARM11_REGCACHE_COUNT (20 + \
- 23 * ARM11_REGCACHE_MODEREGS + \
- 9 * ARM11_REGCACHE_FREGS)
+#define ARM11_REGCACHE_COUNT 1
#define ARM11_TAP_DEFAULT TAP_INVALID
-
-#define CHECK_RETVAL(action) \
-do { \
- int __retval = (action); \
- \
- if (__retval != ERROR_OK) \
- { \
- LOG_DEBUG("error while calling \"" # action "\""); \
- return __retval; \
- } \
- \
-} while (0)
-
-
-struct arm11_register_history
-{
- uint32_t value;
- uint8_t valid;
-};
+#define CHECK_RETVAL(action) \
+ do { \
+ int __retval = (action); \
+ if (__retval != ERROR_OK) { \
+ LOG_DEBUG("error while calling \"%s\"", \
+ # action ); \
+ return __retval; \
+ } \
+ } while (0)
enum arm11_debug_version
{
struct arm11_common
{
struct arm arm;
- struct target * target; /**< Reference back to the owner */
- /** \name Processor type detection */
- /*@{*/
-
- uint32_t device_id; /**< IDCODE readout */
- uint32_t didr; /**< DIDR readout (debug capabilities) */
- uint8_t implementor; /**< DIDR Implementor readout */
+ /** Debug module state. */
+ struct arm_dpm dpm;
size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
-
- enum arm11_debug_version
- debug_version; /**< ARM debug architecture from DIDR */
- /*@}*/
+ size_t free_brps; /**< Number of breakpoints allocated */
uint32_t last_dscr; /**< Last retrieved DSCR value;
Use only for debug message generation */
+ uint32_t saved_rdtr;
+ uint32_t saved_wdtr;
+
+ bool is_rdtr_saved;
+ bool is_wdtr_saved;
+
bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
- /** \name Shadow registers to save processor state */
+ /** \name Shadow registers to save debug state */
/*@{*/
struct reg * reg_list; /**< target register list */
/*@}*/
- struct arm11_register_history
- reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
-
- size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
- size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
// GA
struct reg_cache *core_cache;
struct target * target;
};
-int arm11_register_commands(struct command_context *cmd_ctx);
-
-int arm11_read_etm(struct arm11_common * arm11, uint8_t address, uint32_t *value);
-int arm11_write_etm(struct arm11_common * arm11, uint8_t address, uint32_t value);
-
-
-
#endif /* ARM11_H */