};
-typedef struct arm11_reg_defs_s
+struct arm11_reg_defs
{
char * name;
uint32_t num;
int gdb_num;
enum arm11_regtype type;
-} arm11_reg_defs_t;
+};
/* update arm11_regcache_ids when changing this */
-static const arm11_reg_defs_t arm11_reg_defs[] =
+static const struct arm11_reg_defs arm11_reg_defs[] =
{
{"r0", 0, 0, ARM11_REGISTER_CORE},
{"r1", 1, 1, ARM11_REGISTER_CORE},
};
-static int arm11_on_enter_debug_state(arm11_common_t *arm11);
+static int arm11_on_enter_debug_state(struct arm11_common *arm11);
static int arm11_step(struct target_s *target, int current,
uint32_t address, int handle_breakpoints);
/* helpers */
static int arm11_set_reg(reg_t *reg, uint8_t *buf);
static int arm11_get_reg(reg_t *reg);
-static void arm11_record_register_history(arm11_common_t * arm11);
-static void arm11_dump_reg_changes(arm11_common_t * arm11);
+static void arm11_record_register_history(struct arm11_common * arm11);
+static void arm11_dump_reg_changes(struct arm11_common * arm11);
/** Check and if necessary take control of the system
* available a pointer to a word holding the
* DSCR can be passed. Otherwise use NULL.
*/
-static int arm11_check_init(arm11_common_t *arm11, uint32_t *dscr)
+static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
{
FNC_INFO;
* or on other occasions that stop the processor.
*
*/
-static int arm11_on_enter_debug_state(arm11_common_t *arm11)
+static int arm11_on_enter_debug_state(struct arm11_common *arm11)
{
int retval;
FNC_INFO;
return ERROR_OK;
}
-void arm11_dump_reg_changes(arm11_common_t * arm11)
+void arm11_dump_reg_changes(struct arm11_common * arm11)
{
if (!(debug_level >= LOG_LVL_DEBUG))
* This is called in preparation for the RESTART function.
*
*/
-static int arm11_leave_debug_state(arm11_common_t *arm11)
+static int arm11_leave_debug_state(struct arm11_common *arm11)
{
FNC_INFO;
int retval;
return ERROR_OK;
}
-static void arm11_record_register_history(arm11_common_t *arm11)
+static void arm11_record_register_history(struct arm11_common *arm11)
{
for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
FNC_INFO;
int retval;
- arm11_common_t * arm11 = target->arch_info;
+ struct arm11_common * arm11 = target->arch_info;
uint32_t dscr;
/* architecture specific status reply */
static int arm11_arch_state(struct target_s *target)
{
- arm11_common_t * arm11 = target->arch_info;
+ struct arm11_common * arm11 = target->arch_info;
LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
{
FNC_INFO;
- arm11_common_t * arm11 = target->arch_info;
+ struct arm11_common * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
target_state_name(target));
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
- arm11_common_t * arm11 = target->arch_info;
+ struct arm11_common * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
target_state_name(target));
for (bp = target->breakpoints; bp; bp = bp->next)
{
- arm11_sc7_action_t brp[2];
+ struct arm11_sc7_action brp[2];
brp[0].write = 1;
brp[0].address = ARM11_SC7_BVR0 + brp_num;
static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
{
- arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+ struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
reg=armv4_5_to_arm11(reg);
static void arm11_sim_set_reg(struct arm_sim_interface *sim,
int reg, uint32_t value)
{
- arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+ struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
reg=armv4_5_to_arm11(reg);
static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim,
int pos, int bits)
{
- arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+ struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
}
static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
{
-// arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+// struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
/* FIX!!!! we should implement thumb for arm11 */
return ARMV4_5_STATE_ARM;
static void arm11_sim_set_state(struct arm_sim_interface *sim,
enum armv4_5_state mode)
{
-// arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+// struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
/* FIX!!!! we should implement thumb for arm11 */
LOG_ERROR("Not implemetned!");
static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
{
- //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+ //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
/* FIX!!!! we should implement something that returns the current mode here!!! */
return ARMV4_5_MODE_USR;
return ERROR_TARGET_NOT_HALTED;
}
- arm11_common_t * arm11 = target->arch_info;
+ struct arm11_common * arm11 = target->arch_info;
if (!current)
R(PC) = address;
/* Set up breakpoint for stepping */
- arm11_sc7_action_t brp[2];
+ struct arm11_sc7_action brp[2];
brp[0].write = 1;
brp[0].address = ARM11_SC7_BVR0;
FNC_INFO;
int retval;
- arm11_common_t * arm11 = target->arch_info;
+ struct arm11_common * arm11 = target->arch_info;
retval = arm11_check_init(arm11, NULL);
if (retval != ERROR_OK)
return retval;
{
FNC_INFO;
- arm11_common_t * arm11 = target->arch_info;
+ struct arm11_common * arm11 = target->arch_info;
*reg_list_size = ARM11_GDB_REGISTER_COUNT;
*reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
- arm11_common_t * arm11 = target->arch_info;
+ struct arm11_common * arm11 = target->arch_info;
retval = arm11_run_instr_data_prepare(arm11);
if (retval != ERROR_OK)
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
- arm11_common_t * arm11 = target->arch_info;
+ struct arm11_common * arm11 = target->arch_info;
retval = arm11_run_instr_data_prepare(arm11);
if (retval != ERROR_OK)
{
FNC_INFO;
- arm11_common_t * arm11 = target->arch_info;
+ struct arm11_common * arm11 = target->arch_info;
#if 0
if (breakpoint->type == BKPT_SOFT)
{
FNC_INFO;
- arm11_common_t * arm11 = target->arch_info;
+ struct arm11_common * arm11 = target->arch_info;
arm11->free_brps++;
/* target algorithm support */
static int arm11_run_algorithm(struct target_s *target,
int num_mem_params, struct mem_param *mem_params,
- int num_reg_params, reg_param_t *reg_params,
+ int num_reg_params, struct reg_param *reg_params,
uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info)
{
- arm11_common_t *arm11 = target->arch_info;
+ struct arm11_common *arm11 = target->arch_info;
// enum armv4_5_state core_state = arm11->core_state;
// enum armv4_5_mode core_mode = arm11->core_mode;
uint32_t context[16];
{
FNC_INFO;
- NEW(arm11_common_t, arm11, 1);
+ NEW(struct arm11_common, arm11, 1);
arm11->target = target;
FNC_INFO;
- arm11_common_t * arm11 = target->arch_info;
+ struct arm11_common * arm11 = target->arch_info;
/* check IDCODE */
{
FNC_INFO;
- target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
+ target_t * target = ((struct arm11_reg_state *)reg->arch_info)->target;
if (target->state != TARGET_HALTED)
{
/** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
#if 0
- arm11_common_t *arm11 = target->arch_info;
- const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
+ struct arm11_common *arm11 = target->arch_info;
+ const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
#endif
return ERROR_OK;
{
FNC_INFO;
- target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
- arm11_common_t *arm11 = target->arch_info;
-// const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
+ target_t * target = ((struct arm11_reg_state *)reg->arch_info)->target;
+ struct arm11_common *arm11 = target->arch_info;
+// const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
- arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
+ arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
reg->valid = 1;
reg->dirty = 1;
static int arm11_build_reg_cache(target_t *target)
{
- arm11_common_t *arm11 = target->arch_info;
+ struct arm11_common *arm11 = target->arch_info;
NEW(reg_cache_t, cache, 1);
NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
- NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
+ NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT);
if (arm11_regs_arch_type == -1)
arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
reg_t * r = reg_list + i;
- const arm11_reg_defs_t * rd = arm11_reg_defs + i;
- arm11_reg_state_t * rs = arm11_reg_states + i;
+ const struct arm11_reg_defs * rd = arm11_reg_defs + i;
+ struct arm11_reg_state * rs = arm11_reg_states + i;
r->name = rd->name;
r->size = 32;
0xFFFFFFFF, /* value */
};
-static arm11_common_t * arm11_find_target(const char * arg)
+static struct arm11_common * arm11_find_target(const char * arg)
{
struct jtag_tap * tap;
target_t * t;
return ERROR_FAIL;
}
- arm11_common_t * arm11 = target->arch_info;
+ struct arm11_common * arm11 = target->arch_info;
uint32_t instr = 0xEE000010 |
(cpnum << 8) |
return ERROR_COMMAND_SYNTAX_ERROR;
}
- arm11_common_t * arm11 = arm11_find_target(args[0]);
+ struct arm11_common * arm11 = arm11_find_target(args[0]);
if (!arm11)
{