-/***************************************************************************\r
- * Copyright (C) 2008 digenius technology GmbH. *\r
- * *\r
- * This program is free software; you can redistribute it and/or modify *\r
- * it under the terms of the GNU General Public License as published by *\r
- * the Free Software Foundation; either version 2 of the License, or *\r
- * (at your option) any later version. *\r
- * *\r
- * This program is distributed in the hope that it will be useful, *\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
- * GNU General Public License for more details. *\r
- * *\r
- * You should have received a copy of the GNU General Public License *\r
- * along with this program; if not, write to the *\r
- * Free Software Foundation, Inc., *\r
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
- ***************************************************************************/\r
-\r
-#ifdef HAVE_CONFIG_H\r
-#include "config.h"\r
-#endif\r
-\r
-#include "arm11.h"\r
-#include "jtag.h"\r
-#include "log.h"\r
-\r
-#include <stdlib.h>\r
-#include <string.h>\r
-\r
-#if 0\r
-#define _DEBUG_INSTRUCTION_EXECUTION_\r
-#endif\r
-\r
-\r
-#if 0\r
-#define FNC_INFO DEBUG("-")\r
-#else\r
-#define FNC_INFO\r
-#endif\r
-\r
-#if 1\r
-#define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)\r
-#else\r
-#define FNC_INFO_NOTIMPLEMENTED\r
-#endif\r
-\r
-static void arm11_on_enter_debug_state(arm11_common_t * arm11);\r
-\r
-\r
-#define ARM11_HANDLER(x) \\r
- .x = arm11_##x\r
-\r
-target_type_t arm11_target =\r
-{\r
- .name = "arm11",\r
-\r
- ARM11_HANDLER(poll),\r
- ARM11_HANDLER(arch_state),\r
-\r
- ARM11_HANDLER(target_request_data),\r
-\r
- ARM11_HANDLER(halt),\r
- ARM11_HANDLER(resume),\r
- ARM11_HANDLER(step),\r
-\r
- ARM11_HANDLER(assert_reset),\r
- ARM11_HANDLER(deassert_reset),\r
- ARM11_HANDLER(soft_reset_halt),\r
- ARM11_HANDLER(prepare_reset_halt),\r
- \r
- ARM11_HANDLER(get_gdb_reg_list),\r
- \r
- ARM11_HANDLER(read_memory),\r
- ARM11_HANDLER(write_memory),\r
- \r
- ARM11_HANDLER(bulk_write_memory),\r
- \r
- ARM11_HANDLER(checksum_memory),\r
-\r
- ARM11_HANDLER(add_breakpoint),\r
- ARM11_HANDLER(remove_breakpoint),\r
- ARM11_HANDLER(add_watchpoint),\r
- ARM11_HANDLER(remove_watchpoint),\r
-\r
- ARM11_HANDLER(run_algorithm),\r
- \r
- ARM11_HANDLER(register_commands),\r
- ARM11_HANDLER(target_command),\r
- ARM11_HANDLER(init_target),\r
- ARM11_HANDLER(quit),\r
-};\r
-\r
-int arm11_regs_arch_type = -1;\r
-\r
-\r
-enum arm11_regtype\r
-{\r
- ARM11_REGISTER_CORE,\r
- ARM11_REGISTER_CPSR,\r
-\r
- ARM11_REGISTER_FX,\r
- ARM11_REGISTER_FPS,\r
-\r
- ARM11_REGISTER_FIQ,\r
- ARM11_REGISTER_SVC,\r
- ARM11_REGISTER_ABT,\r
- ARM11_REGISTER_IRQ,\r
- ARM11_REGISTER_UND,\r
- ARM11_REGISTER_MON,\r
-\r
- ARM11_REGISTER_SPSR_FIQ,\r
- ARM11_REGISTER_SPSR_SVC,\r
- ARM11_REGISTER_SPSR_ABT,\r
- ARM11_REGISTER_SPSR_IRQ,\r
- ARM11_REGISTER_SPSR_UND,\r
- ARM11_REGISTER_SPSR_MON,\r
-\r
- /* debug regs */\r
- ARM11_REGISTER_DSCR,\r
- ARM11_REGISTER_WDTR,\r
- ARM11_REGISTER_RDTR,\r
-};\r
-\r
-\r
-typedef struct arm11_reg_defs_s\r
-{\r
- char * name;\r
- u32 num;\r
- int gdb_num;\r
- enum arm11_regtype type;\r
-} arm11_reg_defs_t;\r
-\r
-/* update arm11_regcache_ids when changing this */\r
-static const arm11_reg_defs_t arm11_reg_defs[] =\r
-{\r
- {"r0", 0, 0, ARM11_REGISTER_CORE},\r
- {"r1", 1, 1, ARM11_REGISTER_CORE},\r
- {"r2", 2, 2, ARM11_REGISTER_CORE},\r
- {"r3", 3, 3, ARM11_REGISTER_CORE},\r
- {"r4", 4, 4, ARM11_REGISTER_CORE},\r
- {"r5", 5, 5, ARM11_REGISTER_CORE},\r
- {"r6", 6, 6, ARM11_REGISTER_CORE},\r
- {"r7", 7, 7, ARM11_REGISTER_CORE},\r
- {"r8", 8, 8, ARM11_REGISTER_CORE},\r
- {"r9", 9, 9, ARM11_REGISTER_CORE},\r
- {"r10", 10, 10, ARM11_REGISTER_CORE},\r
- {"r11", 11, 11, ARM11_REGISTER_CORE},\r
- {"r12", 12, 12, ARM11_REGISTER_CORE},\r
- {"sp", 13, 13, ARM11_REGISTER_CORE},\r
- {"lr", 14, 14, ARM11_REGISTER_CORE},\r
- {"pc", 15, 15, ARM11_REGISTER_CORE},\r
-\r
-#if ARM11_REGCACHE_FREGS\r
- {"f0", 0, 16, ARM11_REGISTER_FX},\r
- {"f1", 1, 17, ARM11_REGISTER_FX},\r
- {"f2", 2, 18, ARM11_REGISTER_FX},\r
- {"f3", 3, 19, ARM11_REGISTER_FX},\r
- {"f4", 4, 20, ARM11_REGISTER_FX},\r
- {"f5", 5, 21, ARM11_REGISTER_FX},\r
- {"f6", 6, 22, ARM11_REGISTER_FX},\r
- {"f7", 7, 23, ARM11_REGISTER_FX},\r
- {"fps", 0, 24, ARM11_REGISTER_FPS},\r
-#endif\r
-\r
- {"cpsr", 0, 25, ARM11_REGISTER_CPSR},\r
-\r
-#if ARM11_REGCACHE_MODEREGS\r
- {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},\r
- {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},\r
- {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},\r
- {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},\r
- {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},\r
- {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},\r
- {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},\r
- {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},\r
-\r
- {"r13_svc", 13, -1, ARM11_REGISTER_SVC},\r
- {"r14_svc", 14, -1, ARM11_REGISTER_SVC},\r
- {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},\r
-\r
- {"r13_abt", 13, -1, ARM11_REGISTER_ABT},\r
- {"r14_abt", 14, -1, ARM11_REGISTER_ABT},\r
- {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},\r
-\r
- {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},\r
- {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},\r
- {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},\r
-\r
- {"r13_und", 13, -1, ARM11_REGISTER_UND},\r
- {"r14_und", 14, -1, ARM11_REGISTER_UND},\r
- {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},\r
-\r
- /* ARM1176 only */\r
- {"r13_mon", 13, -1, ARM11_REGISTER_MON},\r
- {"r14_mon", 14, -1, ARM11_REGISTER_MON},\r
- {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},\r
-#endif\r
-\r
- /* Debug Registers */\r
- {"dscr", 0, -1, ARM11_REGISTER_DSCR},\r
- {"wdtr", 0, -1, ARM11_REGISTER_WDTR},\r
- {"rdtr", 0, -1, ARM11_REGISTER_RDTR},\r
-};\r
-\r
-enum arm11_regcache_ids\r
-{\r
- ARM11_RC_R0,\r
- ARM11_RC_RX = ARM11_RC_R0,\r
-\r
- ARM11_RC_R1,\r
- ARM11_RC_R2,\r
- ARM11_RC_R3,\r
- ARM11_RC_R4,\r
- ARM11_RC_R5,\r
- ARM11_RC_R6,\r
- ARM11_RC_R7,\r
- ARM11_RC_R8,\r
- ARM11_RC_R9,\r
- ARM11_RC_R10,\r
- ARM11_RC_R11,\r
- ARM11_RC_R12,\r
- ARM11_RC_R13,\r
- ARM11_RC_SP = ARM11_RC_R13,\r
- ARM11_RC_R14,\r
- ARM11_RC_LR = ARM11_RC_R14,\r
- ARM11_RC_R15,\r
- ARM11_RC_PC = ARM11_RC_R15,\r
-\r
-#if ARM11_REGCACHE_FREGS\r
- ARM11_RC_F0,\r
- ARM11_RC_FX = ARM11_RC_F0,\r
- ARM11_RC_F1,\r
- ARM11_RC_F2,\r
- ARM11_RC_F3,\r
- ARM11_RC_F4,\r
- ARM11_RC_F5,\r
- ARM11_RC_F6,\r
- ARM11_RC_F7,\r
- ARM11_RC_FPS,\r
-#endif\r
-\r
- ARM11_RC_CPSR,\r
-\r
-#if ARM11_REGCACHE_MODEREGS\r
- ARM11_RC_R8_FIQ,\r
- ARM11_RC_R9_FIQ,\r
- ARM11_RC_R10_FIQ,\r
- ARM11_RC_R11_FIQ,\r
- ARM11_RC_R12_FIQ,\r
- ARM11_RC_R13_FIQ,\r
- ARM11_RC_R14_FIQ,\r
- ARM11_RC_SPSR_FIQ,\r
-\r
- ARM11_RC_R13_SVC,\r
- ARM11_RC_R14_SVC,\r
- ARM11_RC_SPSR_SVC,\r
-\r
- ARM11_RC_R13_ABT,\r
- ARM11_RC_R14_ABT,\r
- ARM11_RC_SPSR_ABT,\r
-\r
- ARM11_RC_R13_IRQ,\r
- ARM11_RC_R14_IRQ,\r
- ARM11_RC_SPSR_IRQ,\r
-\r
- ARM11_RC_R13_UND,\r
- ARM11_RC_R14_UND,\r
- ARM11_RC_SPSR_UND,\r
-\r
- ARM11_RC_R13_MON,\r
- ARM11_RC_R14_MON,\r
- ARM11_RC_SPSR_MON,\r
-#endif\r
-\r
- ARM11_RC_DSCR,\r
- ARM11_RC_WDTR,\r
- ARM11_RC_RDTR,\r
-\r
-\r
- ARM11_RC_MAX,\r
-};\r
-\r
-#define ARM11_GDB_REGISTER_COUNT 26\r
-\r
-u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};\r
-\r
-reg_t arm11_gdb_dummy_fp_reg =\r
-{\r
- "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0\r
-};\r
-\r
-u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};\r
-\r
-reg_t arm11_gdb_dummy_fps_reg =\r
-{\r
- "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0\r
-};\r
-\r
-\r
-\r
-/** Check and if necessary take control of the system\r
- *\r
- * \param arm11 Target state variable.\r
- * \param dscr If the current DSCR content is\r
- * available a pointer to a word holding the\r
- * DSCR can be passed. Otherwise use NULL.\r
- */\r
-void arm11_check_init(arm11_common_t * arm11, u32 * dscr)\r
-{\r
- FNC_INFO;\r
-\r
- u32 dscr_local_tmp_copy;\r
-\r
- if (!dscr)\r
- {\r
- dscr = &dscr_local_tmp_copy;\r
- *dscr = arm11_read_DSCR(arm11);\r
- }\r
-\r
- if (!(*dscr & ARM11_DSCR_MODE_SELECT))\r
- {\r
- DEBUG("Bringing target into debug mode");\r
-\r
- *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */\r
- arm11_write_DSCR(arm11, *dscr);\r
-\r
- /* add further reset initialization here */\r
-\r
- if (*dscr & ARM11_DSCR_CORE_HALTED)\r
- {\r
- arm11->target->state = TARGET_HALTED;\r
- arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);\r
- }\r
- else\r
- {\r
- arm11->target->state = TARGET_RUNNING;\r
- arm11->target->debug_reason = DBG_REASON_NOTHALTED;\r
- }\r
-\r
- arm11_sc7_clear_bw(arm11);\r
- }\r
-}\r
-\r
-\r
-\r
-#define R(x) \\r
- (arm11->reg_values[ARM11_RC_##x])\r
-\r
-/** Save processor state.\r
- *\r
- * This is called when the HALT instruction has succeeded\r
- * or on other occasions that stop the processor.\r
- *\r
- */\r
-static void arm11_on_enter_debug_state(arm11_common_t * arm11)\r
-{\r
- FNC_INFO;\r
-\r
- {size_t i;\r
- for(i = 0; i < asizeof(arm11->reg_values); i++)\r
- {\r
- arm11->reg_list[i].valid = 1;\r
- arm11->reg_list[i].dirty = 0;\r
- }}\r
-\r
- /* Save DSCR */\r
-\r
- R(DSCR) = arm11_read_DSCR(arm11);\r
-\r
- /* Save wDTR */\r
-\r
- if (R(DSCR) & ARM11_DSCR_WDTR_FULL)\r
- {\r
- arm11_add_debug_SCAN_N(arm11, 0x05, -1);\r
-\r
- arm11_add_IR(arm11, ARM11_INTEST, -1);\r
-\r
- scan_field_t chain5_fields[3];\r
-\r
- arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);\r
- arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);\r
- arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);\r
-\r
- jtag_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);\r
- }\r
- else\r
- {\r
- arm11->reg_list[ARM11_RC_WDTR].valid = 0;\r
- }\r
-\r
-\r
- /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */\r
- /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs\r
- ARM1136 seems to require this to issue ITR's as well */\r
-\r
- u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;\r
-\r
- /* this executes JTAG queue: */ \r
-\r
- arm11_write_DSCR(arm11, new_dscr);\r
-\r
-// jtag_execute_queue();\r
-\r
-\r
-\r
-// DEBUG("SAVE DSCR %08x", R(DSCR));\r
-\r
-// if (R(DSCR) & ARM11_DSCR_WDTR_FULL)\r
-// DEBUG("SAVE wDTR %08x", R(WDTR));\r
-\r
-\r
- /* From the spec:\r
- Before executing any instruction in debug state you have to drain the write buffer.\r
- This ensures that no imprecise Data Aborts can return at a later point:*/\r
-\r
- /** \todo TODO: Test drain write buffer. */\r
-\r
-#if 0\r
- while (1)\r
- {\r
- /* MRC p14,0,R0,c5,c10,0 */\r
-// arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);\r
-\r
- /* mcr 15, 0, r0, cr7, cr10, {4} */\r
- arm11_run_instr_no_data1(arm11, 0xee070f9a);\r
- \r
- u32 dscr = arm11_read_DSCR(arm11);\r
-\r
- DEBUG("DRAIN, DSCR %08x", dscr);\r
-\r
- if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)\r
- {\r
- arm11_run_instr_no_data1(arm11, 0xe320f000);\r
-\r
- dscr = arm11_read_DSCR(arm11);\r
-\r
- DEBUG("DRAIN, DSCR %08x (DONE)", dscr);\r
-\r
- break;\r
- }\r
- }\r
-#endif\r
-\r
-\r
- arm11_run_instr_data_prepare(arm11);\r
-\r
- /* save r0 - r14 */\r
-\r
-\r
- /** \todo TODO: handle other mode registers */\r
-\r
- {size_t i;\r
- for (i = 0; i < 15; i++)\r
- {\r
- /* MCR p14,0,R?,c0,c5,0 */\r
- arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);\r
- }}\r
-\r
-\r
- /* save rDTR */\r
-\r
- /* check rDTRfull in DSCR */\r
-\r
- if (R(DSCR) & ARM11_DSCR_RDTR_FULL)\r
- {\r
- /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */\r
- arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));\r
- }\r
- else\r
- {\r
- arm11->reg_list[ARM11_RC_RDTR].valid = 0;\r
- }\r
-\r
- /* save CPSR */\r
-\r
- /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */\r
- arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));\r
-\r
- /* save PC */\r
-\r
- /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */\r
- arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));\r
-\r
- /* adjust PC depending on ARM state */\r
-\r
- if (R(CPSR) & ARM11_CPSR_J) /* Java state */\r
- {\r
- arm11->reg_values[ARM11_RC_PC] -= 0;\r
- }\r
- else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */\r
- {\r
- arm11->reg_values[ARM11_RC_PC] -= 4;\r
- }\r
- else /* ARM state */\r
- {\r
- arm11->reg_values[ARM11_RC_PC] -= 8;\r
- }\r
-\r
-// DEBUG("SAVE PC %08x", R(PC));\r
-\r
- arm11_run_instr_data_finish(arm11);\r
-\r
-\r
- {size_t i;\r
- for(i = 0; i < ARM11_REGCACHE_COUNT; i++)\r
- {\r
- if (!arm11->reg_list[i].valid)\r
- {\r
- if (arm11->reg_history[i].valid)\r
- INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);\r
- }\r
- else\r
- {\r
- if (arm11->reg_history[i].valid)\r
- {\r
- if (arm11->reg_history[i].value != arm11->reg_values[i])\r
- INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);\r
- }\r
- else\r
- {\r
- INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);\r
- }\r
- }\r
- }}\r
-}\r
-\r
-\r
-/** Restore processor state\r
- *\r
- * This is called in preparation for the RESTART function.\r
- *\r
- */\r
-void arm11_leave_debug_state(arm11_common_t * arm11)\r
-{\r
- FNC_INFO;\r
-\r
- arm11_run_instr_data_prepare(arm11);\r
-\r
- /** \todo TODO: handle other mode registers */\r
-\r
- /* restore R1 - R14 */\r
- {size_t i;\r
- for (i = 1; i < 15; i++)\r
- {\r
- if (!arm11->reg_list[ARM11_RC_RX + i].dirty)\r
- continue;\r
-\r
- /* MRC p14,0,r?,c0,c5,0 */\r
- arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));\r
-\r
-// DEBUG("RESTORE R%d %08x", i, R(RX + i));\r
- }}\r
-\r
- arm11_run_instr_data_finish(arm11);\r
-\r
-\r
- /* spec says clear wDTR and rDTR; we assume they are clear as\r
- otherwide out programming would be sloppy */\r
-\r
- {\r
- u32 DSCR = arm11_read_DSCR(arm11);\r
-\r
- if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))\r
- {\r
- ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);\r
- }\r
- }\r
-\r
- arm11_run_instr_data_prepare(arm11);\r
-\r
- /* restore original wDTR */\r
-\r
- if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)\r
- {\r
- /* MCR p14,0,R0,c0,c5,0 */\r
- arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));\r
- }\r
-\r
- /* restore CPSR */\r
-\r
- /* MSR CPSR,R0*/\r
- arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));\r
-\r
-\r
- /* restore PC */\r
-\r
- /* MOV PC,R0 */\r
- arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));\r
-\r
-\r
- /* restore R0 */\r
-\r
- /* MRC p14,0,r0,c0,c5,0 */\r
- arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));\r
-\r
- arm11_run_instr_data_finish(arm11);\r
-\r
-\r
- /* restore DSCR */\r
-\r
- arm11_write_DSCR(arm11, R(DSCR));\r
-\r
-\r
- /* restore rDTR */\r
- \r
- if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)\r
- {\r
- arm11_add_debug_SCAN_N(arm11, 0x05, -1);\r
-\r
- arm11_add_IR(arm11, ARM11_EXTEST, -1);\r
-\r
- scan_field_t chain5_fields[3];\r
-\r
- u8 Ready = 0; /* ignored */\r
- u8 Valid = 0; /* ignored */\r
-\r
- arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);\r
- arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);\r
- arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);\r
-\r
- jtag_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);\r
- }\r
-\r
-\r
- {size_t i;\r
- for(i = 0; i < ARM11_REGCACHE_COUNT; i++)\r
- {\r
- arm11->reg_history[i].value = arm11->reg_values[i];\r
- arm11->reg_history[i].valid = arm11->reg_list[i].valid;\r
-\r
- arm11->reg_list[i].valid = 0;\r
- arm11->reg_list[i].dirty = 0;\r
- }}\r
-}\r
-\r
-\r
-/* poll current target status */\r
-int arm11_poll(struct target_s *target)\r
-{\r
- FNC_INFO;\r
-\r
- arm11_common_t * arm11 = target->arch_info;\r
-\r
- if (arm11->trst_active)\r
- return ERROR_OK;\r
-\r
- u32 dscr = arm11_read_DSCR(arm11);\r
-\r
- DEBUG("DSCR %08x", dscr);\r
-\r
- arm11_check_init(arm11, &dscr);\r
-\r
- if (dscr & ARM11_DSCR_CORE_HALTED)\r
- {\r
-// DEBUG("CH %d", target->state);\r
-\r
- if (target->state != TARGET_HALTED)\r
- {\r
- DEBUG("enter TARGET_HALTED");\r
- target->state = TARGET_HALTED;\r
- target->debug_reason = arm11_get_DSCR_debug_reason(dscr);\r
- arm11_on_enter_debug_state(arm11);\r
- }\r
- }\r
- else\r
- {\r
-// DEBUG("CR %d", target->state);\r
-\r
- if (target->state != TARGET_RUNNING)\r
- {\r
- DEBUG("enter TARGET_RUNNING");\r
- target->state = TARGET_RUNNING;\r
- target->debug_reason = DBG_REASON_NOTHALTED;\r
- }\r
- }\r
-\r
- return ERROR_OK;\r
-}\r
-/* architecture specific status reply */\r
-int arm11_arch_state(struct target_s *target)\r
-{\r
- FNC_INFO_NOTIMPLEMENTED;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-\r
-/* target request support */\r
-int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)\r
-{\r
- FNC_INFO_NOTIMPLEMENTED;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-\r
-\r
-/* target execution control */\r
-int arm11_halt(struct target_s *target)\r
-{\r
- FNC_INFO;\r
-\r
- arm11_common_t * arm11 = target->arch_info;\r
-\r
- DEBUG("target->state: %s", target_state_strings[target->state]);\r
-\r
- if (target->state == TARGET_HALTED)\r
- {\r
- WARNING("target was already halted");\r
- return ERROR_TARGET_ALREADY_HALTED;\r
- }\r
-\r
- if (arm11->trst_active)\r
- {\r
- arm11->halt_requested = true;\r
- return ERROR_OK;\r
- }\r
-\r
- arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);\r
-\r
- jtag_execute_queue();\r
-\r
- u32 dscr;\r
-\r
- while (1)\r
- {\r
- dscr = arm11_read_DSCR(arm11);\r
-\r
- if (dscr & ARM11_DSCR_CORE_HALTED)\r
- break;\r
- }\r
-\r
- arm11_on_enter_debug_state(arm11);\r
-\r
- target->state = TARGET_HALTED;\r
- target->debug_reason = arm11_get_DSCR_debug_reason(dscr);\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-\r
-int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)\r
-{\r
- FNC_INFO;\r
-\r
- arm11_common_t * arm11 = target->arch_info;\r
-\r
- DEBUG("target->state: %s", target_state_strings[target->state]);\r
-\r
- if (target->state != TARGET_HALTED)\r
- {\r
- WARNING("target was not halted");\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
-\r
- if (!current)\r
- R(PC) = address;\r
-\r
- target->state = TARGET_RUNNING;\r
- target->debug_reason = DBG_REASON_NOTHALTED;\r
-\r
- arm11_leave_debug_state(arm11);\r
-\r
- arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);\r
-\r
- jtag_execute_queue();\r
-\r
- while (1)\r
- {\r
- u32 dscr = arm11_read_DSCR(arm11);\r
-\r
- DEBUG("DSCR %08x", dscr);\r
-\r
- if (dscr & ARM11_DSCR_CORE_RESTARTED)\r
- break;\r
- }\r
-\r
- DEBUG("RES %d", target->state);\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)\r
-{\r
- FNC_INFO;\r
-\r
- DEBUG("target->state: %s", target_state_strings[target->state]);\r
-\r
- if (target->state != TARGET_HALTED)\r
- {\r
- WARNING("target was not halted");\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
-\r
- arm11_common_t * arm11 = target->arch_info;\r
-\r
- /** \todo TODO: check if break-/watchpoints make any sense at all in combination\r
- * with this. */\r
-\r
- /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively\r
- the VCR might be something worth looking into. */\r
-\r
- /* Set up breakpoint for stepping */\r
-\r
- arm11_sc7_action_t brp[2];\r
-\r
- brp[0].write = 1;\r
- brp[0].address = ARM11_SC7_BVR0;\r
- brp[0].value = R(PC);\r
- brp[1].write = 1;\r
- brp[1].address = ARM11_SC7_BCR0;\r
- brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);\r
-\r
- arm11_sc7_run(arm11, brp, asizeof(brp));\r
-\r
- /* resume */\r
-\r
- arm11_leave_debug_state(arm11);\r
-\r
- arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);\r
-\r
- jtag_execute_queue();\r
-\r
- /** \todo TODO: add a timeout */\r
-\r
- /* wait for halt */\r
-\r
- while (1)\r
- {\r
- u32 dscr = arm11_read_DSCR(arm11);\r
-\r
- DEBUG("DSCR %08x", dscr);\r
-\r
- if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==\r
- (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))\r
- break;\r
- }\r
-\r
-\r
- /* clear breakpoint */\r
-\r
- arm11_sc7_clear_bw(arm11);\r
-\r
-\r
- /* save state */\r
-\r
- arm11_on_enter_debug_state(arm11);\r
-\r
-// target->state = TARGET_HALTED;\r
- target->debug_reason = DBG_REASON_SINGLESTEP;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-\r
-/* target reset control */\r
-int arm11_assert_reset(struct target_s *target)\r
-{\r
- FNC_INFO;\r
-\r
-#if 0\r
- /* assert reset lines */\r
- /* resets only the DBGTAP, not the ARM */\r
-\r
- jtag_add_reset(1, 0);\r
- jtag_add_sleep(5000);\r
-\r
- arm11_common_t * arm11 = target->arch_info;\r
- arm11->trst_active = true;\r
-#endif\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm11_deassert_reset(struct target_s *target)\r
-{\r
- FNC_INFO;\r
-\r
-#if 0\r
- DEBUG("target->state: %s", target_state_strings[target->state]);\r
-\r
- /* deassert reset lines */\r
- jtag_add_reset(0, 0);\r
-\r
- arm11_common_t * arm11 = target->arch_info;\r
- arm11->trst_active = false;\r
-\r
- if (arm11->halt_requested)\r
- return arm11_halt(target);\r
-#endif\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm11_soft_reset_halt(struct target_s *target)\r
-{\r
- FNC_INFO_NOTIMPLEMENTED;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm11_prepare_reset_halt(struct target_s *target)\r
-{\r
- FNC_INFO_NOTIMPLEMENTED;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-\r
-/* target register access for gdb */\r
-int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)\r
-{\r
- FNC_INFO;\r
-\r
- arm11_common_t * arm11 = target->arch_info;\r
-\r
- if (target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
- \r
- *reg_list_size = ARM11_GDB_REGISTER_COUNT;\r
- *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);\r
-\r
- {size_t i;\r
- for (i = 16; i < 24; i++)\r
- {\r
- (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;\r
- }}\r
-\r
- (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;\r
-\r
-\r
- {size_t i;\r
- for (i = 0; i < ARM11_REGCACHE_COUNT; i++)\r
- {\r
- if (arm11_reg_defs[i].gdb_num == -1)\r
- continue;\r
-\r
- (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;\r
- }}\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-\r
-/* target memory access \r
-* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)\r
-* count: number of items of <size>\r
-*/\r
-int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)\r
-{\r
- /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */\r
-\r
- FNC_INFO;\r
-\r
- DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);\r
-\r
- arm11_common_t * arm11 = target->arch_info;\r
-\r
- arm11_run_instr_data_prepare(arm11);\r
-\r
- /* MRC p14,0,r0,c0,c5,0 */\r
- arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);\r
-\r
- switch (size)\r
- {\r
- case 1:\r
- /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */\r
- arm11->reg_list[ARM11_RC_R1].dirty = 1;\r
-\r
- while (count--)\r
- {\r
- /* ldrb r1, [r0], #1 */\r
- arm11_run_instr_no_data1(arm11, 0xe4d01001);\r
-\r
- u32 res;\r
- /* MCR p14,0,R1,c0,c5,0 */\r
- arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);\r
-\r
- *buffer++ = res;\r
- }\r
- break;\r
-\r
- case 2:\r
- {\r
- arm11->reg_list[ARM11_RC_R1].dirty = 1;\r
-\r
- u16 * buf16 = (u16*)buffer;\r
-\r
- while (count--)\r
- {\r
- /* ldrh r1, [r0], #2 */\r
- arm11_run_instr_no_data1(arm11, 0xe0d010b2);\r
-\r
- u32 res;\r
-\r
- /* MCR p14,0,R1,c0,c5,0 */\r
- arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);\r
-\r
- *buf16++ = res;\r
- }\r
- break;\r
- }\r
-\r
- case 4:\r
-\r
- /* LDC p14,c5,[R0],#4 */\r
- arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);\r
- break;\r
- }\r
-\r
- arm11_run_instr_data_finish(arm11);\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)\r
-{\r
- FNC_INFO;\r
-\r
- DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);\r
-\r
- arm11_common_t * arm11 = target->arch_info;\r
-\r
- arm11_run_instr_data_prepare(arm11);\r
-\r
- /* MRC p14,0,r0,c0,c5,0 */\r
- arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);\r
-\r
- switch (size)\r
- {\r
- case 1:\r
- arm11->reg_list[ARM11_RC_R1].dirty = 1;\r
-\r
- while (count--)\r
- {\r
- /* MRC p14,0,r1,c0,c5,0 */\r
- arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);\r
-\r
- /* strb r1, [r0], #1 */\r
- arm11_run_instr_no_data1(arm11, 0xe4c01001);\r
- }\r
- break;\r
-\r
- case 2:\r
- {\r
- arm11->reg_list[ARM11_RC_R1].dirty = 1;\r
-\r
- u16 * buf16 = (u16*)buffer;\r
-\r
- while (count--)\r
- {\r
- /* MRC p14,0,r1,c0,c5,0 */\r
- arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);\r
-\r
- /* strh r1, [r0], #2 */\r
- arm11_run_instr_no_data1(arm11, 0xe0c010b2);\r
- }\r
- break;\r
- }\r
-\r
- case 4:\r
- /** \todo TODO: check if buffer cast to u32* might cause alignment problems */\r
-\r
- /* STC p14,c5,[R0],#4 */\r
- arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);\r
- break;\r
- }\r
-\r
- arm11_run_instr_data_finish(arm11);\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-\r
-/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */\r
-int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)\r
-{\r
- FNC_INFO;\r
-\r
- return arm11_write_memory(target, address, 4, count, buffer);\r
-}\r
-\r
-\r
-int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)\r
-{\r
- FNC_INFO_NOTIMPLEMENTED;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-\r
-/* target break-/watchpoint control \r
-* rw: 0 = write, 1 = read, 2 = access\r
-*/\r
-int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)\r
-{\r
- FNC_INFO_NOTIMPLEMENTED;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)\r
-{\r
- FNC_INFO_NOTIMPLEMENTED;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)\r
-{\r
- FNC_INFO_NOTIMPLEMENTED;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)\r
-{\r
- FNC_INFO_NOTIMPLEMENTED;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-\r
-/* target algorithm support */\r
-int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)\r
-{\r
- FNC_INFO_NOTIMPLEMENTED;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-\r
-int arm11_register_commands(struct command_context_s *cmd_ctx)\r
-{\r
- FNC_INFO;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)\r
-{\r
- FNC_INFO;\r
-\r
- if (argc < 4)\r
- {\r
- ERROR("'target arm11' 4th argument <jtag chain pos>");\r
- exit(-1);\r
- }\r
-\r
- int chain_pos = strtoul(args[3], NULL, 0);\r
-\r
- NEW(arm11_common_t, arm11, 1);\r
-\r
- arm11->target = target;\r
-\r
- /* prepare JTAG information for the new target */\r
- arm11->jtag_info.chain_pos = chain_pos;\r
- arm11->jtag_info.scann_size = 5;\r
-\r
- arm_jtag_setup_connection(&arm11->jtag_info);\r
-\r
- jtag_device_t *device = jtag_get_device(chain_pos);\r
-\r
- if (device->ir_length != 5)\r
- {\r
- ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");\r
- exit(-1);\r
- }\r
-\r
- target->arch_info = arm11;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)\r
-{\r
- FNC_INFO;\r
-\r
- arm11_common_t * arm11 = target->arch_info;\r
-\r
- /* check IDCODE */\r
-\r
- arm11_add_IR(arm11, ARM11_IDCODE, -1);\r
-\r
- scan_field_t idcode_field;\r
-\r
- arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);\r
-\r
- jtag_add_dr_scan_vc(1, &idcode_field, TAP_PD);\r
-\r
- /* check DIDR */\r
-\r
- arm11_add_debug_SCAN_N(arm11, 0x00, -1);\r
-\r
- arm11_add_IR(arm11, ARM11_INTEST, -1);\r
-\r
- scan_field_t chain0_fields[2];\r
-\r
- arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);\r
- arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);\r
-\r
- jtag_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);\r
-\r
- jtag_execute_queue();\r
-\r
-\r
- switch (arm11->device_id & 0x0FFFF000)\r
- {\r
- case 0x07B36000: INFO("found ARM1136"); break;\r
- case 0x07B56000: INFO("found ARM1156"); break;\r
- case 0x07B76000: INFO("found ARM1176"); break;\r
- default:\r
- {\r
- ERROR("'target arm11' expects IDCODE 0x*7B*7****");\r
- exit(-1);\r
- }\r
- }\r
-\r
- arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;\r
- arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;\r
-\r
-\r
- DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",\r
- arm11->device_id,\r
- arm11->implementor,\r
- arm11->didr);\r
-\r
- arm11_build_reg_cache(target);\r
-\r
-\r
- /* as a side-effect this reads DSCR and thus\r
- * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag\r
- * as suggested by the spec.\r
- */\r
-\r
- arm11_check_init(arm11, NULL);\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm11_quit(void)\r
-{\r
- FNC_INFO_NOTIMPLEMENTED;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-/** Load a register that is marked !valid in the register cache */\r
-int arm11_get_reg(reg_t *reg)\r
-{\r
- FNC_INFO;\r
-\r
- target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;\r
-\r
- if (target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
-\r
- /** \todo TODO: Check this. We assume that all registers are fetched debug entry. */\r
-\r
-#if 0\r
- arm11_common_t *arm11 = target->arch_info;\r
- const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;\r
-#endif\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-/** Change a value in the register cache */\r
-int arm11_set_reg(reg_t *reg, u8 *buf)\r
-{\r
- FNC_INFO;\r
-\r
- target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;\r
- arm11_common_t *arm11 = target->arch_info;\r
-// const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;\r
-\r
- arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);\r
- reg->valid = 1;\r
- reg->dirty = 1;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-\r
-void arm11_build_reg_cache(target_t *target)\r
-{\r
- arm11_common_t *arm11 = target->arch_info;\r
-\r
- NEW(reg_cache_t, cache, 1);\r
- NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);\r
- NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);\r
-\r
- if (arm11_regs_arch_type == -1)\r
- arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);\r
-\r
- arm11->reg_list = reg_list;\r
-\r
- /* Build the process context cache */ \r
- cache->name = "arm11 registers";\r
- cache->next = NULL;\r
- cache->reg_list = reg_list;\r
- cache->num_regs = ARM11_REGCACHE_COUNT;\r
-\r
- reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);\r
- (*cache_p) = cache;\r
-\r
-// armv7m->core_cache = cache;\r
-// armv7m->process_context = cache;\r
-\r
- size_t i;\r
-\r
- /* Not very elegant assertion */\r
- if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||\r
- ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||\r
- ARM11_REGCACHE_COUNT != ARM11_RC_MAX)\r
- {\r
- ERROR("arm11->reg_values inconsistent (%d %d %d %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);\r
- exit(-1);\r
- }\r
-\r
- for (i = 0; i < ARM11_REGCACHE_COUNT; i++)\r
- {\r
- reg_t * r = reg_list + i;\r
- const arm11_reg_defs_t * rd = arm11_reg_defs + i;\r
- arm11_reg_state_t * rs = arm11_reg_states + i;\r
-\r
- r->name = rd->name;\r
- r->size = 32;\r
- r->value = (u8 *)(arm11->reg_values + i);\r
- r->dirty = 0;\r
- r->valid = 0;\r
- r->bitfield_desc = NULL;\r
- r->num_bitfields = 0;\r
- r->arch_type = arm11_regs_arch_type;\r
- r->arch_info = rs;\r
-\r
- rs->def_index = i;\r
- rs->target = target;\r
- }\r
-}\r
-\r
-#if 0\r
- arm11_run_instr_data_prepare(arm11);\r
-\r
- /* MRC p14,0,r0,c0,c5,0 */\r
- arm11_run_instr_data_to_core(arm11, 0xee100e15, 0xCA00003C);\r
- /* MRC p14,0,r1,c0,c5,0 */\r
- arm11_run_instr_data_to_core(arm11, 0xee101e15, 0xFFFFFFFF);\r
-\r
- arm11_run_instr_data_finish(arm11);\r
-#endif\r
-\r
-\r
+/***************************************************************************
+ * Copyright (C) 2008 digenius technology GmbH. *
+ * Michael Bruck *
+ * *
+ * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
+ * *
+ * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
+ * *
+ * Copyright (C) 2009 David Brownell *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "etm.h"
+#include "breakpoints.h"
+#include "arm11_dbgtap.h"
+#include "arm_simulator.h"
+#include <helper/time_support.h>
+#include "target_type.h"
+#include "algorithm.h"
+#include "register.h"
+#include "arm_opcodes.h"
+
+#if 0
+#define _DEBUG_INSTRUCTION_EXECUTION_
+#endif
+
+
+static int arm11_step(struct target *target, int current,
+ uint32_t address, int handle_breakpoints);
+
+
+/** Check and if necessary take control of the system
+ *
+ * \param arm11 Target state variable.
+ */
+static int arm11_check_init(struct arm11_common *arm11)
+{
+ CHECK_RETVAL(arm11_read_DSCR(arm11));
+
+ if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) {
+ LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
+ LOG_DEBUG("Bringing target into debug mode");
+
+ arm11->dscr |= DSCR_HALT_DBG_MODE;
+ CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
+
+ /* add further reset initialization here */
+
+ arm11->simulate_reset_on_next_halt = true;
+
+ if (arm11->dscr & DSCR_CORE_HALTED) {
+ /** \todo TODO: this needs further scrutiny because
+ * arm11_debug_entry() never gets called. (WHY NOT?)
+ * As a result we don't read the actual register states from
+ * the target.
+ */
+
+ arm11->arm.target->state = TARGET_HALTED;
+ arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
+ } else {
+ arm11->arm.target->state = TARGET_RUNNING;
+ arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
+ }
+
+ CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
+ }
+
+ return ERROR_OK;
+}
+
+/**
+ * Save processor state. This is called after a HALT instruction
+ * succeeds, and on other occasions the processor enters debug mode
+ * (breakpoint, watchpoint, etc). Caller has updated arm11->dscr.
+ */
+static int arm11_debug_entry(struct arm11_common *arm11)
+{
+ int retval;
+
+ arm11->arm.target->state = TARGET_HALTED;
+ arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
+
+ /* REVISIT entire cache should already be invalid !!! */
+ register_cache_invalidate(arm11->arm.core_cache);
+
+ /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
+
+ /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
+ arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
+ if (arm11->is_wdtr_saved) {
+ arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
+
+ arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+
+ struct scan_field chain5_fields[3];
+
+ arm11_setup_field(arm11, 32, NULL,
+ &arm11->saved_wdtr, chain5_fields + 0);
+ arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
+ arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
+
+ arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
+ chain5_fields), chain5_fields, TAP_DRPAUSE);
+
+ }
+
+ /* DSCR: set the Execute ARM instruction enable bit.
+ *
+ * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
+ * but not to issue ITRs(?). The ARMv7 arch spec says it's required
+ * for executing instructions via ITR.
+ */
+ CHECK_RETVAL(arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr));
+
+
+ /* From the spec:
+ Before executing any instruction in debug state you have to drain the write buffer.
+ This ensures that no imprecise Data Aborts can return at a later point:*/
+
+ /** \todo TODO: Test drain write buffer. */
+
+#if 0
+ while (1) {
+ /* MRC p14,0,R0,c5,c10,0 */
+ /* arm11_run_instr_no_data1(arm11, / *0xee150e1a* /0xe320f000); */
+
+ /* mcr 15, 0, r0, cr7, cr10, {4} */
+ arm11_run_instr_no_data1(arm11, 0xee070f9a);
+
+ uint32_t dscr = arm11_read_DSCR(arm11);
+
+ LOG_DEBUG("DRAIN, DSCR %08x", dscr);
+
+ if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) {
+ arm11_run_instr_no_data1(arm11, 0xe320f000);
+
+ dscr = arm11_read_DSCR(arm11);
+
+ LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
+
+ break;
+ }
+ }
+#endif
+
+ /* Save registers.
+ *
+ * NOTE: ARM1136 TRM suggests saving just R0 here now, then
+ * CPSR and PC after the rDTR stuff. We do it all at once.
+ */
+ retval = arm_dpm_read_current_registers(&arm11->dpm);
+ if (retval != ERROR_OK)
+ LOG_ERROR("DPM REG READ -- fail");
+
+ retval = arm11_run_instr_data_prepare(arm11);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
+ arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
+ if (arm11->is_rdtr_saved) {
+ /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
+ retval = arm11_run_instr_data_from_core_via_r0(arm11,
+ 0xEE100E15, &arm11->saved_rdtr);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ /* REVISIT Now that we've saved core state, there's may also
+ * be MMU and cache state to care about ...
+ */
+
+ if (arm11->simulate_reset_on_next_halt) {
+ arm11->simulate_reset_on_next_halt = false;
+
+ LOG_DEBUG("Reset c1 Control Register");
+
+ /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
+
+ /* MCR p15,0,R0,c1,c0,0 */
+ retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ }
+
+ if (arm11->arm.target->debug_reason == DBG_REASON_WATCHPOINT) {
+ uint32_t wfar;
+
+ /* MRC p15, 0, <Rd>, c6, c0, 1 ; Read WFAR */
+ retval = arm11_run_instr_data_from_core_via_r0(arm11,
+ ARMV4_5_MRC(15, 0, 0, 6, 0, 1),
+ &wfar);
+ if (retval != ERROR_OK)
+ return retval;
+ arm_dpm_report_wfar(arm11->arm.dpm, wfar);
+ }
+
+
+ retval = arm11_run_instr_data_finish(arm11);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+/**
+ * Restore processor state. This is called in preparation for
+ * the RESTART function.
+ */
+static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
+{
+ int retval;
+
+ /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */
+
+ /* NOTE: the ARM1136 TRM suggests restoring all registers
+ * except R0/PC/CPSR right now. Instead, we do them all
+ * at once, just a bit later on.
+ */
+
+ /* REVISIT once we start caring about MMU and cache state,
+ * address it here ...
+ */
+
+ /* spec says clear wDTR and rDTR; we assume they are clear as
+ otherwise our programming would be sloppy */
+ {
+ CHECK_RETVAL(arm11_read_DSCR(arm11));
+
+ if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL)) {
+ /*
+ The wDTR/rDTR two registers that are used to send/receive data to/from
+ the core in tandem with corresponding instruction codes that are
+ written into the core. The RDTR FULL/WDTR FULL flag indicates that the
+ registers hold data that was written by one side (CPU or JTAG) and not
+ read out by the other side.
+ */
+ LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)",
+ (unsigned) arm11->dscr);
+ return ERROR_FAIL;
+ }
+ }
+
+ /* maybe restore original wDTR */
+ if (arm11->is_wdtr_saved) {
+ retval = arm11_run_instr_data_prepare(arm11);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* MCR p14,0,R0,c0,c5,0 */
+ retval = arm11_run_instr_data_to_core_via_r0(arm11,
+ 0xee000e15, arm11->saved_wdtr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = arm11_run_instr_data_finish(arm11);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ /* restore CPSR, PC, and R0 ... after flushing any modified
+ * registers.
+ */
+ CHECK_RETVAL(arm_dpm_write_dirty_registers(&arm11->dpm, bpwp));
+
+ CHECK_RETVAL(arm11_bpwp_flush(arm11));
+
+ register_cache_invalidate(arm11->arm.core_cache);
+
+ /* restore DSCR */
+ CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
+
+ /* maybe restore rDTR */
+ if (arm11->is_rdtr_saved) {
+ arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
+
+ arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
+
+ struct scan_field chain5_fields[3];
+
+ uint8_t Ready = 0; /* ignored */
+ uint8_t Valid = 0; /* ignored */
+
+ arm11_setup_field(arm11, 32, &arm11->saved_rdtr,
+ NULL, chain5_fields + 0);
+ arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
+ arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
+
+ arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
+ chain5_fields), chain5_fields, TAP_DRPAUSE);
+ }
+
+ /* now processor is ready to RESTART */
+
+ return ERROR_OK;
+}
+
+/* poll current target status */
+static int arm11_poll(struct target *target)
+{
+ int retval;
+ struct arm11_common *arm11 = target_to_arm11(target);
+
+ CHECK_RETVAL(arm11_check_init(arm11));
+
+ if (arm11->dscr & DSCR_CORE_HALTED) {
+ if (target->state != TARGET_HALTED) {
+ enum target_state old_state = target->state;
+
+ LOG_DEBUG("enter TARGET_HALTED");
+ retval = arm11_debug_entry(arm11);
+ if (retval != ERROR_OK)
+ return retval;
+
+ target_call_event_callbacks(target,
+ (old_state == TARGET_DEBUG_RUNNING)
+ ? TARGET_EVENT_DEBUG_HALTED
+ : TARGET_EVENT_HALTED);
+ }
+ } else {
+ if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) {
+ LOG_DEBUG("enter TARGET_RUNNING");
+ target->state = TARGET_RUNNING;
+ target->debug_reason = DBG_REASON_NOTHALTED;
+ }
+ }
+
+ return ERROR_OK;
+}
+/* architecture specific status reply */
+static int arm11_arch_state(struct target *target)
+{
+ struct arm11_common *arm11 = target_to_arm11(target);
+ int retval;
+
+ retval = arm_arch_state(target);
+
+ /* REVISIT also display ARM11-specific MMU and cache status ... */
+
+ if (target->debug_reason == DBG_REASON_WATCHPOINT)
+ LOG_USER("Watchpoint triggered at PC %#08x",
+ (unsigned) arm11->dpm.wp_pc);
+
+ return retval;
+}
+
+/* target execution control */
+static int arm11_halt(struct target *target)
+{
+ struct arm11_common *arm11 = target_to_arm11(target);
+
+ LOG_DEBUG("target->state: %s",
+ target_state_name(target));
+
+ if (target->state == TARGET_UNKNOWN)
+ arm11->simulate_reset_on_next_halt = true;
+
+ if (target->state == TARGET_HALTED) {
+ LOG_DEBUG("target was already halted");
+ return ERROR_OK;
+ }
+
+ arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
+
+ CHECK_RETVAL(jtag_execute_queue());
+
+ int i = 0;
+
+ while (1) {
+ CHECK_RETVAL(arm11_read_DSCR(arm11));
+
+ if (arm11->dscr & DSCR_CORE_HALTED)
+ break;
+
+
+ long long then = 0;
+ if (i == 1000)
+ then = timeval_ms();
+ if (i >= 1000) {
+ if ((timeval_ms()-then) > 1000) {
+ LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+ i++;
+ }
+
+ enum target_state old_state = target->state;
+
+ CHECK_RETVAL(arm11_debug_entry(arm11));
+
+ CHECK_RETVAL(
+ target_call_event_callbacks(target,
+ old_state ==
+ TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
+
+ return ERROR_OK;
+}
+
+static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
+{
+ void *value = arm11->arm.pc->value;
+
+ if (!current)
+ buf_set_u32(value, 0, 32, address);
+ else
+ address = buf_get_u32(value, 0, 32);
+
+ return address;
+}
+
+static int arm11_resume(struct target *target, int current,
+ uint32_t address, int handle_breakpoints, int debug_execution)
+{
+ /* LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", */
+ /* current, address, handle_breakpoints, debug_execution); */
+
+ struct arm11_common *arm11 = target_to_arm11(target);
+
+ LOG_DEBUG("target->state: %s",
+ target_state_name(target));
+
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ address = arm11_nextpc(arm11, current, address);
+
+ LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
+
+ /* clear breakpoints/watchpoints and VCR*/
+ CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
+
+ if (!debug_execution)
+ target_free_all_working_areas(target);
+
+ /* Should we skip over breakpoints matching the PC? */
+ if (handle_breakpoints) {
+ struct breakpoint *bp;
+
+ for (bp = target->breakpoints; bp; bp = bp->next) {
+ if (bp->address == address) {
+ LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
+ arm11_step(target, 1, 0, 0);
+ break;
+ }
+ }
+ }
+
+ /* activate all breakpoints */
+ if (true) {
+ struct breakpoint *bp;
+ unsigned brp_num = 0;
+
+ for (bp = target->breakpoints; bp; bp = bp->next) {
+ struct arm11_sc7_action brp[2];
+
+ brp[0].write = 1;
+ brp[0].address = ARM11_SC7_BVR0 + brp_num;
+ brp[0].value = bp->address;
+ brp[1].write = 1;
+ brp[1].address = ARM11_SC7_BCR0 + brp_num;
+ brp[1].value = 0x1 |
+ (3 <<
+ 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
+
+ CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
+
+ LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
+ bp->address);
+
+ brp_num++;
+ }
+
+ if (arm11->vcr)
+ CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
+ }
+
+ /* activate all watchpoints and breakpoints */
+ CHECK_RETVAL(arm11_leave_debug_state(arm11, true));
+
+ arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
+
+ CHECK_RETVAL(jtag_execute_queue());
+
+ int i = 0;
+ while (1) {
+ CHECK_RETVAL(arm11_read_DSCR(arm11));
+
+ LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
+
+ if (arm11->dscr & DSCR_CORE_RESTARTED)
+ break;
+
+
+ long long then = 0;
+ if (i == 1000)
+ then = timeval_ms();
+ if (i >= 1000) {
+ if ((timeval_ms()-then) > 1000) {
+ LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+ i++;
+ }
+
+ target->debug_reason = DBG_REASON_NOTHALTED;
+ if (!debug_execution)
+ target->state = TARGET_RUNNING;
+ else
+ target->state = TARGET_DEBUG_RUNNING;
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
+
+ return ERROR_OK;
+}
+
+static int arm11_step(struct target *target, int current,
+ uint32_t address, int handle_breakpoints)
+{
+ LOG_DEBUG("target->state: %s",
+ target_state_name(target));
+
+ if (target->state != TARGET_HALTED) {
+ LOG_WARNING("target was not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ struct arm11_common *arm11 = target_to_arm11(target);
+
+ address = arm11_nextpc(arm11, current, address);
+
+ LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : "");
+
+
+ /** \todo TODO: Thumb not supported here */
+
+ uint32_t next_instruction;
+
+ CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
+
+ /* skip over BKPT */
+ if ((next_instruction & 0xFFF00070) == 0xe1200070) {
+ address = arm11_nextpc(arm11, 0, address + 4);
+ LOG_DEBUG("Skipping BKPT %08" PRIx32, address);
+ }
+ /* skip over Wait for interrupt / Standby
+ * mcr 15, 0, r?, cr7, cr0, {4} */
+ else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) {
+ address = arm11_nextpc(arm11, 0, address + 4);
+ LOG_DEBUG("Skipping WFI %08" PRIx32, address);
+ }
+ /* ignore B to self */
+ else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
+ LOG_DEBUG("Not stepping jump to self");
+ else {
+ /** \todo TODO: check if break-/watchpoints make any sense at all in combination
+ * with this. */
+
+ /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
+ * the VCR might be something worth looking into. */
+
+
+ /* Set up breakpoint for stepping */
+
+ struct arm11_sc7_action brp[2];
+
+ brp[0].write = 1;
+ brp[0].address = ARM11_SC7_BVR0;
+ brp[1].write = 1;
+ brp[1].address = ARM11_SC7_BCR0;
+
+ if (arm11->hardware_step) {
+ /* Hardware single stepping ("instruction address
+ * mismatch") is used if enabled. It's not quite
+ * exactly "run one instruction"; "branch to here"
+ * loops won't break, neither will some other cases,
+ * but it's probably the best default.
+ *
+ * Hardware single stepping isn't supported on v6
+ * debug modules. ARM1176 and v7 can support it...
+ *
+ * FIXME Thumb stepping likely needs to use 0x03
+ * or 0xc0 byte masks, not 0x0f.
+ */
+ brp[0].value = address;
+ brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
+ | (0 << 14) | (0 << 16) | (0 << 20)
+ | (2 << 21);
+ } else {
+ /* Sets a breakpoint on the next PC, as calculated
+ * by instruction set simulation.
+ *
+ * REVISIT stepping Thumb on ARM1156 requires Thumb2
+ * support from the simulator.
+ */
+ uint32_t next_pc;
+ int retval;
+
+ retval = arm_simulate_step(target, &next_pc);
+ if (retval != ERROR_OK)
+ return retval;
+
+ brp[0].value = next_pc;
+ brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
+ | (0 << 14) | (0 << 16) | (0 << 20)
+ | (0 << 21);
+ }
+
+ CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
+
+ /* resume */
+
+
+ if (arm11->step_irq_enable)
+ /* this disable should be redundant ... */
+ arm11->dscr &= ~DSCR_INT_DIS;
+ else
+ arm11->dscr |= DSCR_INT_DIS;
+
+
+ CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
+
+ arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
+
+ CHECK_RETVAL(jtag_execute_queue());
+
+ /* wait for halt */
+ int i = 0;
+
+ while (1) {
+ const uint32_t mask = DSCR_CORE_RESTARTED
+ | DSCR_CORE_HALTED;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11));
+ LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
+
+ if ((arm11->dscr & mask) == mask)
+ break;
+
+ long long then = 0;
+ if (i == 1000)
+ then = timeval_ms();
+ if (i >= 1000) {
+ if ((timeval_ms()-then) > 1000) {
+ LOG_WARNING(
+ "Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+ i++;
+ }
+
+ /* clear breakpoint */
+ CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
+
+ /* save state */
+ CHECK_RETVAL(arm11_debug_entry(arm11));
+
+ /* restore default state */
+ arm11->dscr &= ~DSCR_INT_DIS;
+
+ }
+
+ target->debug_reason = DBG_REASON_SINGLESTEP;
+
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
+
+ return ERROR_OK;
+}
+
+static int arm11_assert_reset(struct target *target)
+{
+ struct arm11_common *arm11 = target_to_arm11(target);
+
+ /* optionally catch reset vector */
+ if (target->reset_halt && !(arm11->vcr & 1))
+ CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1));
+
+ /* Issue some kind of warm reset. */
+ if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
+ target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
+ else if (jtag_get_reset_config() & RESET_HAS_SRST) {
+ /* REVISIT handle "pulls" cases, if there's
+ * hardware that needs them to work.
+ */
+ jtag_add_reset(0, 1);
+ } else {
+ LOG_ERROR("%s: how to reset?", target_name(target));
+ return ERROR_FAIL;
+ }
+
+ /* registers are now invalid */
+ register_cache_invalidate(arm11->arm.core_cache);
+
+ target->state = TARGET_RESET;
+
+ return ERROR_OK;
+}
+
+/*
+ * - There is another bug in the arm11 core. (iMX31 specific again?)
+ * When you generate an access to external logic (for example DDR
+ * controller via AHB bus) and that block is not configured (perhaps
+ * it is still held in reset), that transaction will never complete.
+ * This will hang arm11 core but it will also hang JTAG controller.
+ * Nothing short of srst assertion will bring it out of this.
+ */
+
+static int arm11_deassert_reset(struct target *target)
+{
+ struct arm11_common *arm11 = target_to_arm11(target);
+ int retval;
+
+ /* be certain SRST is off */
+ jtag_add_reset(0, 0);
+
+ /* WORKAROUND i.MX31 problems: SRST goofs the TAP, and resets
+ * at least DSCR. OMAP24xx doesn't show that problem, though
+ * SRST-only reset seems to be problematic for other reasons.
+ * (Secure boot sequences being one likelihood!)
+ */
+ jtag_add_tlr();
+
+ CHECK_RETVAL(arm11_poll(target));
+
+ if (target->reset_halt) {
+ if (target->state != TARGET_HALTED) {
+ LOG_WARNING("%s: ran after reset and before halt ...",
+ target_name(target));
+ retval = target_halt(target);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+ }
+
+ /* maybe restore vector catch config */
+ if (target->reset_halt && !(arm11->vcr & 1))
+ CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
+
+ return ERROR_OK;
+}
+
+/* target memory access
+ * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
+ * count: number of items of <size>
+ *
+ * arm11_config_memrw_no_increment - in the future we may want to be able
+ * to read/write a range of data to a "port". a "port" is an action on
+ * read memory address for some peripheral.
+ */
+static int arm11_read_memory_inner(struct target *target,
+ uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
+ bool arm11_config_memrw_no_increment)
+{
+ /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment
+ *problems */
+ int retval;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_WARNING("target was not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
+ address,
+ size,
+ count);
+
+ struct arm11_common *arm11 = target_to_arm11(target);
+
+ retval = arm11_run_instr_data_prepare(arm11);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* MRC p14,0,r0,c0,c5,0 */
+ retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
+ if (retval != ERROR_OK)
+ return retval;
+
+ switch (size) {
+ case 1:
+ arm11->arm.core_cache->reg_list[1].dirty = true;
+
+ for (size_t i = 0; i < count; i++) {
+ /* ldrb r1, [r0], #1 */
+ /* ldrb r1, [r0] */
+ CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
+ !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000));
+
+ uint32_t res;
+ /* MCR p14,0,R1,c0,c5,0 */
+ CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
+
+ *buffer++ = res;
+ }
+
+ break;
+
+ case 2:
+ {
+ arm11->arm.core_cache->reg_list[1].dirty = true;
+
+ for (size_t i = 0; i < count; i++) {
+ /* ldrh r1, [r0], #2 */
+ CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
+ !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0));
+
+ uint32_t res;
+
+ /* MCR p14,0,R1,c0,c5,0 */
+ CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
+
+ uint16_t svalue = res;
+ memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
+ }
+
+ break;
+ }
+
+ case 4:
+ {
+ uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
+ /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
+ uint32_t *words = (uint32_t *)(void *)buffer;
+
+ /* LDC p14,c5,[R0],#4 */
+ /* LDC p14,c5,[R0] */
+ CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, instr, words, count));
+ break;
+ }
+ }
+
+ return arm11_run_instr_data_finish(arm11);
+}
+
+static int arm11_read_memory(struct target *target,
+ uint32_t address,
+ uint32_t size,
+ uint32_t count,
+ uint8_t *buffer)
+{
+ return arm11_read_memory_inner(target, address, size, count, buffer, false);
+}
+
+/*
+* no_increment - in the future we may want to be able
+* to read/write a range of data to a "port". a "port" is an action on
+* read memory address for some peripheral.
+*/
+static int arm11_write_memory_inner(struct target *target,
+ uint32_t address, uint32_t size,
+ uint32_t count, const uint8_t *buffer,
+ bool no_increment)
+{
+ int retval;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_WARNING("target was not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
+ address,
+ size,
+ count);
+
+ struct arm11_common *arm11 = target_to_arm11(target);
+
+ retval = arm11_run_instr_data_prepare(arm11);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* load r0 with buffer address
+ * MRC p14,0,r0,c0,c5,0 */
+ retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* burst writes are not used for single words as those may well be
+ * reset init script writes.
+ *
+ * The other advantage is that as burst writes are default, we'll
+ * now exercise both burst and non-burst code paths with the
+ * default settings, increasing code coverage.
+ */
+ bool burst = arm11->memwrite_burst && (count > 1);
+
+ switch (size) {
+ case 1:
+ {
+ arm11->arm.core_cache->reg_list[1].dirty = true;
+
+ for (size_t i = 0; i < count; i++) {
+ /* load r1 from DCC with byte data */
+ /* MRC p14,0,r1,c0,c5,0 */
+ retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* write r1 to memory */
+ /* strb r1, [r0], #1 */
+ /* strb r1, [r0] */
+ retval = arm11_run_instr_no_data1(arm11,
+ !no_increment ? 0xe4c01001 : 0xe5c01000);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ break;
+ }
+
+ case 2:
+ {
+ arm11->arm.core_cache->reg_list[1].dirty = true;
+
+ for (size_t i = 0; i < count; i++) {
+ uint16_t value;
+ memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
+
+ /* load r1 from DCC with halfword data */
+ /* MRC p14,0,r1,c0,c5,0 */
+ retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* write r1 to memory */
+ /* strh r1, [r0], #2 */
+ /* strh r1, [r0] */
+ retval = arm11_run_instr_no_data1(arm11,
+ !no_increment ? 0xe0c010b2 : 0xe1c010b0);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ break;
+ }
+
+ case 4: {
+ /* stream word data through DCC directly to memory */
+ /* increment: STC p14,c5,[R0],#4 */
+ /* no increment: STC p14,c5,[R0]*/
+ uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
+
+ /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
+ uint32_t *words = (uint32_t *)(void *)buffer;
+
+ /* "burst" here just means trusting each instruction executes
+ * fully before we run the next one: per-word roundtrips, to
+ * check the Ready flag, are not used.
+ */
+ if (!burst)
+ retval = arm11_run_instr_data_to_core(arm11,
+ instr, words, count);
+ else
+ retval = arm11_run_instr_data_to_core_noack(arm11,
+ instr, words, count);
+ if (retval != ERROR_OK)
+ return retval;
+
+ break;
+ }
+ }
+
+ /* r0 verification */
+ if (!no_increment) {
+ uint32_t r0;
+
+ /* MCR p14,0,R0,c0,c5,0 */
+ retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (address + size * count != r0) {
+ LOG_ERROR("Data transfer failed. Expected end "
+ "address 0x%08x, got 0x%08x",
+ (unsigned) (address + size * count),
+ (unsigned) r0);
+
+ if (burst)
+ LOG_ERROR(
+ "use 'arm11 memwrite burst disable' to disable fast burst mode");
+
+
+ if (arm11->memwrite_error_fatal)
+ return ERROR_FAIL;
+ }
+ }
+
+ return arm11_run_instr_data_finish(arm11);
+}
+
+static int arm11_write_memory(struct target *target,
+ uint32_t address, uint32_t size,
+ uint32_t count, const uint8_t *buffer)
+{
+ /* pointer increment matters only for multi-unit writes ...
+ * not e.g. to a "reset the chip" controller.
+ */
+ return arm11_write_memory_inner(target, address, size,
+ count, buffer, count == 1);
+}
+
+/* target break-/watchpoint control
+* rw: 0 = write, 1 = read, 2 = access
+*/
+static int arm11_add_breakpoint(struct target *target,
+ struct breakpoint *breakpoint)
+{
+ struct arm11_common *arm11 = target_to_arm11(target);
+
+#if 0
+ if (breakpoint->type == BKPT_SOFT) {
+ LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+#endif
+
+ if (!arm11->free_brps) {
+ LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ if (breakpoint->length != 4) {
+ LOG_DEBUG("only breakpoints of four bytes length supported");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ arm11->free_brps--;
+
+ return ERROR_OK;
+}
+
+static int arm11_remove_breakpoint(struct target *target,
+ struct breakpoint *breakpoint)
+{
+ struct arm11_common *arm11 = target_to_arm11(target);
+
+ arm11->free_brps++;
+
+ return ERROR_OK;
+}
+
+static int arm11_target_create(struct target *target, Jim_Interp *interp)
+{
+ struct arm11_common *arm11;
+
+ if (target->tap == NULL)
+ return ERROR_FAIL;
+
+ if (target->tap->ir_length != 5) {
+ LOG_ERROR("'target arm11' expects IR LENGTH = 5");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ arm11 = calloc(1, sizeof *arm11);
+ if (!arm11)
+ return ERROR_FAIL;
+
+ arm11->arm.core_type = ARM_MODE_ANY;
+ arm_init_arch_info(target, &arm11->arm);
+
+ arm11->jtag_info.tap = target->tap;
+ arm11->jtag_info.scann_size = 5;
+ arm11->jtag_info.scann_instr = ARM11_SCAN_N;
+ arm11->jtag_info.cur_scan_chain = ~0; /* invalid/unknown */
+ arm11->jtag_info.intest_instr = ARM11_INTEST;
+
+ arm11->memwrite_burst = true;
+ arm11->memwrite_error_fatal = true;
+
+ return ERROR_OK;
+}
+
+static int arm11_init_target(struct command_context *cmd_ctx,
+ struct target *target)
+{
+ /* Initialize anything we can set up without talking to the target */
+ return ERROR_OK;
+}
+
+/* talk to the target and set things up */
+static int arm11_examine(struct target *target)
+{
+ int retval;
+ char *type;
+ struct arm11_common *arm11 = target_to_arm11(target);
+ uint32_t didr, device_id;
+ uint8_t implementor;
+
+ /* FIXME split into do-first-time and do-every-time logic ... */
+
+ /* check IDCODE */
+
+ arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
+
+ struct scan_field idcode_field;
+
+ arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
+
+ arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &idcode_field, TAP_DRPAUSE);
+
+ /* check DIDR */
+
+ arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
+
+ arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+
+ struct scan_field chain0_fields[2];
+
+ arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
+ arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
+
+ arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
+ chain0_fields), chain0_fields, TAP_IDLE);
+
+ CHECK_RETVAL(jtag_execute_queue());
+
+ /* assume the manufacturer id is ok; check the part # */
+ switch ((device_id >> 12) & 0xFFFF) {
+ case 0x7B36:
+ type = "ARM1136";
+ break;
+ case 0x7B37:
+ type = "ARM11 MPCore";
+ break;
+ case 0x7B56:
+ type = "ARM1156";
+ break;
+ case 0x7B76:
+ arm11->arm.core_type = ARM_MODE_MON;
+ /* NOTE: could default arm11->hardware_step to true */
+ type = "ARM1176";
+ break;
+ default:
+ LOG_ERROR("unexpected ARM11 ID code");
+ return ERROR_FAIL;
+ }
+ LOG_INFO("found %s", type);
+
+ /* unlikely this could ever fail, but ... */
+ switch ((didr >> 16) & 0x0F) {
+ case ARM11_DEBUG_V6:
+ case ARM11_DEBUG_V61: /* supports security extensions */
+ break;
+ default:
+ LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
+ return ERROR_FAIL;
+ }
+
+ arm11->brp = ((didr >> 24) & 0x0F) + 1;
+
+ /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
+ arm11->free_brps = arm11->brp;
+
+ LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
+ device_id, implementor, didr);
+
+ /* as a side-effect this reads DSCR and thus
+ * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
+ * as suggested by the spec.
+ */
+
+ retval = arm11_check_init(arm11);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Build register cache "late", after target_init(), since we
+ * want to know if this core supports Secure Monitor mode.
+ */
+ if (!target_was_examined(target))
+ CHECK_RETVAL(arm11_dpm_init(arm11, didr));
+
+ /* ETM on ARM11 still uses original scanchain 6 access mode */
+ if (arm11->arm.etm && !target_was_examined(target)) {
+ *register_get_last_cache_p(&target->reg_cache) =
+ etm_build_reg_cache(target, &arm11->jtag_info,
+ arm11->arm.etm);
+ CHECK_RETVAL(etm_setup(target));
+ }
+
+ target_set_examined(target);
+
+ return ERROR_OK;
+}
+
+#define ARM11_BOOL_WRAPPER(name, print_name) \
+ COMMAND_HANDLER(arm11_handle_bool_ ## name) \
+ { \
+ struct target *target = get_current_target(CMD_CTX); \
+ struct arm11_common *arm11 = target_to_arm11(target); \
+ \
+ return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
+ &arm11->name, print_name); \
+ }
+
+ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
+ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
+ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
+ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
+
+/* REVISIT handle the VCR bits like other ARMs: use symbols for
+ * input and output values.
+ */
+
+COMMAND_HANDLER(arm11_handle_vcr)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm11_common *arm11 = target_to_arm11(target);
+
+ switch (CMD_ARGC) {
+ case 0:
+ break;
+ case 1:
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr);
+ break;
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ LOG_INFO("VCR 0x%08" PRIx32 "", arm11->vcr);
+ return ERROR_OK;
+}
+
+static const struct command_registration arm11_mw_command_handlers[] = {
+ {
+ .name = "burst",
+ .handler = arm11_handle_bool_memwrite_burst,
+ .mode = COMMAND_ANY,
+ .help = "Display or modify flag controlling potentially "
+ "risky fast burst mode (default: enabled)",
+ .usage = "['enable'|'disable']",
+ },
+ {
+ .name = "error_fatal",
+ .handler = arm11_handle_bool_memwrite_error_fatal,
+ .mode = COMMAND_ANY,
+ .help = "Display or modify flag controlling transfer "
+ "termination on transfer errors"
+ " (default: enabled)",
+ .usage = "['enable'|'disable']",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration arm11_any_command_handlers[] = {
+ {
+ /* "hardware_step" is only here to check if the default
+ * simulate + breakpoint implementation is broken.
+ * TEMPORARY! NOT DOCUMENTED! */
+ .name = "hardware_step",
+ .handler = arm11_handle_bool_hardware_step,
+ .mode = COMMAND_ANY,
+ .help = "DEBUG ONLY - Hardware single stepping"
+ " (default: disabled)",
+ .usage = "['enable'|'disable']",
+ },
+ {
+ .name = "memwrite",
+ .mode = COMMAND_ANY,
+ .help = "memwrite command group",
+ .usage = "",
+ .chain = arm11_mw_command_handlers,
+ },
+ {
+ .name = "step_irq_enable",
+ .handler = arm11_handle_bool_step_irq_enable,
+ .mode = COMMAND_ANY,
+ .help = "Display or modify flag controlling interrupt "
+ "enable while stepping (default: disabled)",
+ .usage = "['enable'|'disable']",
+ },
+ {
+ .name = "vcr",
+ .handler = arm11_handle_vcr,
+ .mode = COMMAND_ANY,
+ .help = "Display or modify Vector Catch Register",
+ .usage = "[value]",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration arm11_command_handlers[] = {
+ {
+ .chain = arm_command_handlers,
+ },
+ {
+ .chain = etm_command_handlers,
+ },
+ {
+ .name = "arm11",
+ .mode = COMMAND_ANY,
+ .help = "ARM11 command group",
+ .usage = "",
+ .chain = arm11_any_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+/** Holds methods for ARM11xx targets. */
+struct target_type arm11_target = {
+ .name = "arm11",
+
+ .poll = arm11_poll,
+ .arch_state = arm11_arch_state,
+
+ .halt = arm11_halt,
+ .resume = arm11_resume,
+ .step = arm11_step,
+
+ .assert_reset = arm11_assert_reset,
+ .deassert_reset = arm11_deassert_reset,
+
+ .get_gdb_reg_list = arm_get_gdb_reg_list,
+
+ .read_memory = arm11_read_memory,
+ .write_memory = arm11_write_memory,
+
+ .checksum_memory = arm_checksum_memory,
+ .blank_check_memory = arm_blank_check_memory,
+
+ .add_breakpoint = arm11_add_breakpoint,
+ .remove_breakpoint = arm11_remove_breakpoint,
+
+ .run_algorithm = armv4_5_run_algorithm,
+
+ .commands = arm11_command_handlers,
+ .target_create = arm11_target_create,
+ .init_target = arm11_init_target,
+ .examine = arm11_examine,
+};
Code Review / openocd.git / blobdiff