return ERROR_OK;
}
-/** Restore processor state
- *
- * This is called in preparation for the RESTART function.
- *
- */
-static int arm11_leave_debug_state(struct arm11_common *arm11)
+/**
+ * Restore processor state. This is called in preparation for
+ * the RESTART function.
+ */
+static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
{
int retval;
/* restore CPSR, PC, and R0 ... after flushing any modified
* registers.
*/
- retval = arm_dpm_write_dirty_registers(&arm11->dpm);
+ retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
register_cache_invalidate(arm11->arm.core_cache);
arm11_sc7_set_vcr(arm11, arm11_vcr);
}
- arm11_leave_debug_state(arm11);
+ arm11_leave_debug_state(arm11, handle_breakpoints);
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
- CHECK_RETVAL(arm11_leave_debug_state(arm11));
+ CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
}
/*
-* arm11_config_memrw_no_increment - in the future we may want to be able
+* no_increment - in the future we may want to be able
* to read/write a range of data to a "port". a "port" is an action on
* read memory address for some peripheral.
*/
static int arm11_write_memory_inner(struct target *target,
- uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
- bool arm11_config_memrw_no_increment)
+ uint32_t address, uint32_t size,
+ uint32_t count, uint8_t *buffer,
+ bool no_increment)
{
int retval;
/* strb r1, [r0], #1 */
/* strb r1, [r0] */
retval = arm11_run_instr_no_data1(arm11,
- !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
+ !no_increment
+ ? 0xe4c01001
+ : 0xe5c01000);
if (retval != ERROR_OK)
return retval;
}
/* strh r1, [r0], #2 */
/* strh r1, [r0] */
retval = arm11_run_instr_no_data1(arm11,
- !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
+ !no_increment
+ ? 0xe0c010b2
+ : 0xe1c010b0);
if (retval != ERROR_OK)
return retval;
}
}
case 4: {
- uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
+ uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
uint32_t *words = (uint32_t*)buffer;
}
/* r0 verification */
- if (!arm11_config_memrw_no_increment)
+ if (!no_increment)
{
uint32_t r0;
}
static int arm11_write_memory(struct target *target,
- uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+ uint32_t address, uint32_t size,
+ uint32_t count, uint8_t *buffer)
{
- return arm11_write_memory_inner(target, address, size, count, buffer, false);
+ /* pointer increment matters only for multi-unit writes ...
+ * not e.g. to a "reset the chip" controller.
+ */
+ return arm11_write_memory_inner(target, address, size,
+ count, buffer, count == 1);
}
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
return ERROR_OK;
}
-static int arm11_add_watchpoint(struct target *target,
- struct watchpoint *watchpoint)
-{
- LOG_WARNING("Not implemented: %s", __func__);
-
- return ERROR_FAIL;
-}
-
-static int arm11_remove_watchpoint(struct target *target,
- struct watchpoint *watchpoint)
-{
- LOG_WARNING("Not implemented: %s", __func__);
-
- return ERROR_FAIL;
-}
-
static int arm11_target_create(struct target *target, Jim_Interp *interp)
{
struct arm11_common *arm11;
return ERROR_OK;
}
-static const uint32_t arm11_coproc_instruction_limits[] =
-{
- 15, /* coprocessor */
- 7, /* opcode 1 */
- 15, /* CRn */
- 15, /* CRm */
- 7, /* opcode 2 */
- 0xFFFFFFFF, /* value */
-};
-
-static int arm11_mrc_inner(struct target *target, int cpnum,
- uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
- uint32_t *value, bool read)
-{
- int retval;
- struct arm11_common *arm11 = target_to_arm11(target);
-
- if (target->state != TARGET_HALTED)
- {
- LOG_ERROR("Target not halted");
- return ERROR_FAIL;
- }
-
- uint32_t instr = 0xEE000010 |
- (cpnum << 8) |
- (op1 << 21) |
- (CRn << 16) |
- (CRm << 0) |
- (op2 << 5);
-
- if (read)
- instr |= 0x00100000;
-
- retval = arm11_run_instr_data_prepare(arm11);
- if (retval != ERROR_OK)
- return retval;
-
- if (read)
- {
- retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value);
- if (retval != ERROR_OK)
- return retval;
- }
- else
- {
- retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value);
- if (retval != ERROR_OK)
- return retval;
- }
-
- return arm11_run_instr_data_finish(arm11);
-}
-
-static int arm11_mrc(struct target *target, int cpnum,
- uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
-{
- return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true);
-}
-
-static int arm11_mcr(struct target *target, int cpnum,
- uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
-{
- return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
-}
-
static const struct command_registration arm11_mw_command_handlers[] = {
{
.name = "burst",
COMMAND_REGISTRATION_DONE
};
static const struct command_registration arm11_command_handlers[] = {
+ {
+ .chain = arm_command_handlers,
+ },
+ {
+ .chain = etm_command_handlers,
+ },
{
.name = "arm11",
.mode = COMMAND_ANY,
COMMAND_REGISTRATION_DONE
};
-static int arm11_register_commands(struct command_context *cmd_ctx)
-{
- armv4_5_register_commands(cmd_ctx);
- etm_register_commands(cmd_ctx);
- return register_commands(cmd_ctx, NULL, arm11_command_handlers);
-}
-
/** Holds methods for ARM11xx targets. */
struct target_type arm11_target = {
.name = "arm11",
.add_breakpoint = arm11_add_breakpoint,
.remove_breakpoint = arm11_remove_breakpoint,
- .add_watchpoint = arm11_add_watchpoint,
- .remove_watchpoint = arm11_remove_watchpoint,
.run_algorithm = armv4_5_run_algorithm,
- .register_commands = arm11_register_commands,
+ .commands = arm11_command_handlers,
.target_create = arm11_target_create,
.init_target = arm11_init_target,
.examine = arm11_examine,
-
- .mrc = arm11_mrc,
- .mcr = arm11_mcr,
};
Code Review / openocd.git / blobdiff