target/aarch64: Add watchpoint support

[openocd.git] / src / target / arm.h

diff --git a/src/target/arm.h b/src/target/arm.h
index 10a053cedef56bc31247a9dbf0bb9c8494fb4c64..d97a95edf934a0e6fbeeb102e32b62cec7bfb658 100644 (file)
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -40,6 +40,26 @@
  * support has not yet been integrated, affecting Cortex-M parts.
  */
 
+/**
+ * Indicates what registers are in the ARM state core register set.
+ *
+ * - ARM_CORE_TYPE_STD indicates the standard set of 37 registers, seen
+ *   on for example ARM7TDMI cores.
+ * - ARM_CORE_TYPE_SEC_EXT indicates core has security extensions, thus
+ *   three more registers are shadowed for "Secure Monitor" mode.
+ * - ARM_CORE_TYPE_VIRT_EXT indicates core has virtualization extensions
+ *   and also security extensions. Additional shadowed registers for
+ *   "Secure Monitor" and "Hypervisor" modes.
+ * - ARM_CORE_TYPE_M_PROFILE indicates a microcontroller profile core,
+ *   which only shadows SP.
+ */
+enum arm_core_type {
+       ARM_CORE_TYPE_STD = -1,
+       ARM_CORE_TYPE_SEC_EXT = 1,
+       ARM_CORE_TYPE_VIRT_EXT,
+       ARM_CORE_TYPE_M_PROFILE,
+};
+
 /**
  * Represent state of an ARM core.
  *
@@ -60,6 +80,7 @@ enum arm_mode {
        ARM_MODE_SVC = 19,
        ARM_MODE_MON = 22,
        ARM_MODE_ABT = 23,
+       ARM_MODE_HYP = 26,
        ARM_MODE_UND = 27,
        ARM_MODE_1176_MON = 28,
        ARM_MODE_SYS = 31,
@@ -161,15 +182,8 @@ struct arm {
        /** Support for arm_reg_current() */
        const int *map;
 
-       /**
-        * Indicates what registers are in the ARM state core register set.
-        * ARM_MODE_ANY indicates the standard set of 37 registers,
-        * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
-        * more registers are shadowed, for "Secure Monitor" mode.
-        * ARM_MODE_THREAD indicates a microcontroller profile core,
-        * which only shadows SP.
-        */
-       enum arm_mode core_type;
+       /** Indicates what registers are in the ARM state core register set. */
+       enum arm_core_type core_type;
 
        /** Record the current core mode: SVC, USR, or some other mode. */
        enum arm_mode core_mode;
@@ -183,6 +197,9 @@ struct arm {
        /** Flag reporting armv6m based core. */
        bool is_armv6m;
 
+       /** Flag reporting armv8m based core. */
+       bool is_armv8m;
+
        /** Floating point or VFP version, 0 if disabled. */
        int arm_vfp_version;
 
@@ -258,6 +275,8 @@ struct arm_reg {
 };
 
 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
+void arm_free_reg_cache(struct arm *arm);
+
 struct reg_cache *armv8_build_reg_cache(struct target *target);
 
 extern const struct command_registration arm_command_handlers[];
@@ -267,6 +286,7 @@ const char *arm_get_gdb_arch(struct target *target);
 int arm_get_gdb_reg_list(struct target *target,
                struct reg **reg_list[], int *reg_list_size,
                enum target_register_class reg_class);
+const char *armv8_get_gdb_arch(struct target *target);
 int armv8_get_gdb_reg_list(struct target *target,
                struct reg **reg_list[], int *reg_list_size,
                enum target_register_class reg_class);