Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
flash support (only full erase/write) for 568013 and 568037
[openocd.git] / src / flash / nor / stm32x.c
diff --git a/src/flash/nor/stm32x.c b/src/flash/nor/stm32x.c
index ae4f02b55c7dbab61fab1168a9b17202b6ea191e..3914d25c2f4765b86c2b550c1af2483c03686c81 100644 (file)
--- a/src/flash/nor/stm32x.c
+++ b/src/flash/nor/stm32x.c
@@ -25,11 +25,90 @@
 #endif
 
 #include "imp.h"
-#include "stm32x.h"
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
 #include <target/armv7m.h>
 
+/* stm32x register locations */
+
+#define STM32_FLASH_ACR                0x40022000
+#define STM32_FLASH_KEYR       0x40022004
+#define STM32_FLASH_OPTKEYR    0x40022008
+#define STM32_FLASH_SR         0x4002200C
+#define STM32_FLASH_CR         0x40022010
+#define STM32_FLASH_AR         0x40022014
+#define STM32_FLASH_OBR                0x4002201C
+#define STM32_FLASH_WRPR       0x40022020
+
+/* option byte location */
+
+#define STM32_OB_RDP           0x1FFFF800
+#define STM32_OB_USER          0x1FFFF802
+#define STM32_OB_DATA0         0x1FFFF804
+#define STM32_OB_DATA1         0x1FFFF806
+#define STM32_OB_WRP0          0x1FFFF808
+#define STM32_OB_WRP1          0x1FFFF80A
+#define STM32_OB_WRP2          0x1FFFF80C
+#define STM32_OB_WRP3          0x1FFFF80E
+
+/* FLASH_CR register bits */
+
+#define FLASH_PG               (1 << 0)
+#define FLASH_PER              (1 << 1)
+#define FLASH_MER              (1 << 2)
+#define FLASH_OPTPG            (1 << 4)
+#define FLASH_OPTER            (1 << 5)
+#define FLASH_STRT             (1 << 6)
+#define FLASH_LOCK             (1 << 7)
+#define FLASH_OPTWRE   (1 << 9)
+
+/* FLASH_SR register bits */
+
+#define FLASH_BSY              (1 << 0)
+#define FLASH_PGERR            (1 << 2)
+#define FLASH_WRPRTERR (1 << 4)
+#define FLASH_EOP              (1 << 5)
+
+/* STM32_FLASH_OBR bit definitions (reading) */
+
+#define OPT_ERROR              0
+#define OPT_READOUT            1
+#define OPT_RDWDGSW            2
+#define OPT_RDRSTSTOP  3
+#define OPT_RDRSTSTDBY 4
+#define OPT_BFB2               5       /* dual flash bank only */
+
+/* register unlock keys */
+
+#define KEY1                   0x45670123
+#define KEY2                   0xCDEF89AB
+
+/* we use an offset to access the second bank on dual flash devices
+ * strangely the protection of the second bank is done on the bank0 reg's */
+
+#define FLASH_OFFSET_B0        0x00
+#define FLASH_OFFSET_B1 0x40
+
+struct stm32x_options
+{
+       uint16_t RDP;
+       uint16_t user_options;
+       uint16_t protection[4];
+};
+
+struct stm32x_flash_bank
+{
+       struct stm32x_options option_bytes;
+       struct working_area *write_algorithm;
+       int ppage_size;
+       int probed;
+
+       bool has_dual_banks;
+       /* used to access dual flash bank stm32xl
+        * 0x00 will address bank 0 flash
+        * 0x40 will address bank 1 flash */
+       int register_offset;
+};
 
 static int stm32x_mass_erase(struct flash_bank *bank);
 
@@ -50,14 +129,22 @@ FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 
        stm32x_info->write_algorithm = NULL;
        stm32x_info->probed = 0;
+       stm32x_info->has_dual_banks = false;
+       stm32x_info->register_offset = FLASH_OFFSET_B0;
 
        return ERROR_OK;
 }
 
-static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
+static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
+{
+       struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
+       return reg + stm32x_info->register_offset;
+}
+
+static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 {
        struct target *target = bank->target;
-       return target_read_u32(target, STM32_FLASH_SR, status);
+       return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 }
 
 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
@@ -101,11 +188,27 @@ static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
                /* If this operation fails, we ignore it and report the original
                 * retval
                 */
-               target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
+               target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
+                               FLASH_WRPRTERR | FLASH_PGERR);
        }
        return retval;
 }
 
+int stm32x_check_operation_supported(struct flash_bank *bank)
+{
+       struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
+
+       /* if we have a dual flash bank device then
+        * we need to perform option byte stuff on bank0 only */
+       if (stm32x_info->register_offset != FLASH_OFFSET_B0)
+       {
+               LOG_ERROR("Option Byte Operation's must use bank0");
+               return ERROR_FLASH_OPERATION_FAILED;
+       }
+
+       return ERROR_OK;
+}
+
 static int stm32x_read_options(struct flash_bank *bank)
 {
        uint32_t optiondata;
@@ -115,7 +218,9 @@ static int stm32x_read_options(struct flash_bank *bank)
        stm32x_info = bank->driver_priv;
 
        /* read current option bytes */
-       target_read_u32(target, STM32_FLASH_OBR, &optiondata);
+       int retval = target_read_u32(target, STM32_FLASH_OBR, &optiondata);
+       if (retval != ERROR_OK)
+               return retval;
 
        stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
        stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
@@ -124,7 +229,9 @@ static int stm32x_read_options(struct flash_bank *bank)
                LOG_INFO("Device Security Bit Set");
 
        /* each bit refers to a 4bank protection */
-       target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
+       retval = target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
+       if (retval != ERROR_OK)
+               return retval;
 
        stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
        stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
@@ -285,9 +392,15 @@ static int stm32x_protect_check(struct flash_bank *bank)
                return ERROR_TARGET_NOT_HALTED;
        }
 
+       int retval = stm32x_check_operation_supported(bank);
+       if (ERROR_OK != retval)
+               return retval;
+
        /* medium density - each bit refers to a 4bank protection
         * high density - each bit refers to a 2bank protection */
-       target_read_u32(target, STM32_FLASH_WRPR, &protection);
+       retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* medium density - each protection bit is for 4 * 1K pages
         * high density - each protection bit is for 2 * 2K pages */
@@ -358,22 +471,24 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
        }
 
        /* unlock flash registers */
-       int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
+       int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
        if (retval != ERROR_OK)
                return retval;
-       retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
+       retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
        if (retval != ERROR_OK)
                return retval;
 
        for (i = first; i <= last; i++)
        {
-               retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
+               retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
                if (retval != ERROR_OK)
                        return retval;
-               retval = target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
+               retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
+                               bank->base + bank->sectors[i].offset);
                if (retval != ERROR_OK)
                        return retval;
-               retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
+               retval = target_write_u32(target,
+                               stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
                if (retval != ERROR_OK)
                        return retval;
 
@@ -384,7 +499,7 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
                bank->sectors[i].is_erased = 1;
        }
 
-       retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
+       retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
        if (retval != ERROR_OK)
                return retval;
 
@@ -408,17 +523,30 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) &&
-                       (last + 1) % stm32x_info->ppage_size))
+       int retval = stm32x_check_operation_supported(bank);
+       if (ERROR_OK != retval)
+               return retval;
+
+       if ((first % stm32x_info->ppage_size) != 0)
        {
-               LOG_WARNING("Error: start and end sectors must be on a %d sector boundary",
+               LOG_WARNING("aligned start protect sector to a %d sector boundary",
                                stm32x_info->ppage_size);
-               return ERROR_FLASH_SECTOR_INVALID;
+               first = first - (first % stm32x_info->ppage_size);
+       }
+       if (((last + 1) % stm32x_info->ppage_size) != 0)
+       {
+               LOG_WARNING("aligned end protect sector to a %d sector boundary",
+                               stm32x_info->ppage_size);
+               last++;
+               last = last - (last % stm32x_info->ppage_size);
+               last--;
        }
 
        /* medium density - each bit refers to a 4bank protection
         * high density - each bit refers to a 2bank protection */
-       target_read_u32(target, STM32_FLASH_WRPR, &protection);
+       retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
+       if (retval != ERROR_OK)
+               return retval;
 
        prot_reg[0] = (uint16_t)protection;
        prot_reg[1] = (uint16_t)(protection >> 8);
@@ -495,25 +623,27 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
        /* see contib/loaders/flash/stm32x.s for src */
 
        static const uint8_t stm32x_flash_write_code[] = {
+                                                                       /* #define STM32_FLASH_CR_OFFSET        0x10 */
+                                                                       /* #define STM32_FLASH_SR_OFFSET        0x0C */
                                                                        /* write: */
-               0xDF, 0xF8, 0x24, 0x40,         /* ldr  r4, STM32_FLASH_CR */
-               0x09, 0x4D,                                     /* ldr  r5, STM32_FLASH_SR */
-               0x4F, 0xF0, 0x01, 0x03,         /* mov  r3, #1 */
-               0x23, 0x60,                                     /* str  r3, [r4, #0] */
-               0x30, 0xF8, 0x02, 0x3B,         /* ldrh r3, [r0], #2 */
-               0x21, 0xF8, 0x02, 0x3B,         /* strh r3, [r1], #2 */
+               0x08, 0x4c,                                     /* ldr  r4, STM32_FLASH_BASE */
+               0x1c, 0x44,                                     /* add  r4, r3 */
+                                                                       /* write_half_word: */
+               0x01, 0x23,                                     /* movs r3, #0x01 */
+               0x23, 0x61,                                     /* str  r3, [r4, #STM32_FLASH_CR_OFFSET] */
+               0x30, 0xf8, 0x02, 0x3b,         /* ldrh r3, [r0], #0x02 */
+               0x21, 0xf8, 0x02, 0x3b,         /* strh r3, [r1], #0x02 */
                                                                        /* busy: */
-               0x2B, 0x68,                                     /* ldr  r3, [r5, #0] */
-               0x13, 0xF0, 0x01, 0x0F,         /* tst  r3, #0x01 */
-               0xFB, 0xD0,                                     /* beq  busy */
-               0x13, 0xF0, 0x14, 0x0F,         /* tst  r3, #0x14 */
-               0x01, 0xD1,                                     /* bne  exit */
-               0x01, 0x3A,                                     /* subs r2, r2, #1 */
-               0xED, 0xD1,                                     /* bne  write */
+               0xe3, 0x68,                                     /* ldr  r3, [r4, #STM32_FLASH_SR_OFFSET] */
+               0x13, 0xf0, 0x01, 0x0f,         /* tst  r3, #0x01 */
+               0xfb, 0xd0,                                     /* beq  busy */
+               0x13, 0xf0, 0x14, 0x0f,         /* tst  r3, #0x14 */
+               0x01, 0xd1,                                     /* bne  exit */
+               0x01, 0x3a,                                     /* subs r2, r2, #0x01 */
+               0xf0, 0xd1,                                     /* bne  write_half_word */
                                                                        /* exit: */
-               0x00, 0xBE,                             /* bkpt #0 */
-               0x10, 0x20, 0x02, 0x40,         /* STM32_FLASH_CR:      .word 0x40022010 */
-               0x0C, 0x20, 0x02, 0x40          /* STM32_FLASH_SR:      .word 0x4002200C */
+               0x00, 0xbe,                                     /* bkpt #0x00 */
+               0x00, 0x20, 0x02, 0x40,         /* STM32_FLASH_BASE: .word 0x40022000 */
        };
 
        /* flash write code */
@@ -551,7 +681,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
        init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
        init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
        init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
-       init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
+       init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT);
 
        while (count > 0)
        {
@@ -565,6 +695,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
                buf_set_u32(reg_params[0].value, 0, 32, source->address);
                buf_set_u32(reg_params[1].value, 0, 32, address);
                buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
+               buf_set_u32(reg_params[3].value, 0, 32, stm32x_info->register_offset);
 
                if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
                                stm32x_info->write_algorithm->address,
@@ -632,10 +763,10 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
        }
 
        /* unlock flash registers */
-       retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
+       retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
        if (retval != ERROR_OK)
                return retval;
-       retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
+       retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
        if (retval != ERROR_OK)
                return retval;
 
@@ -660,12 +791,15 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
                }
        }
 
+       if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
+               return retval;
+
        while (words_remaining > 0)
        {
                uint16_t value;
                memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
 
-               retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
+               retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
                if (retval != ERROR_OK)
                        return retval;
                retval = target_write_u16(target, address, value);
@@ -686,7 +820,7 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
                uint16_t value = 0xffff;
                memcpy(&value, buffer + bytes_written, bytes_remaining);
 
-               retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
+               retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
                if (retval != ERROR_OK)
                        return retval;
                retval = target_write_u16(target, address, value);
@@ -709,16 +843,22 @@ static int stm32x_probe(struct flash_bank *bank)
        uint16_t num_pages;
        uint32_t device_id;
        int page_size;
+       uint32_t base_address = 0x08000000;
 
        stm32x_info->probed = 0;
+       stm32x_info->register_offset = FLASH_OFFSET_B0;
 
        /* read stm32 device id register */
-       target_read_u32(target, 0xE0042000, &device_id);
+       int retval = target_read_u32(target, 0xE0042000, &device_id);
+       if (retval != ERROR_OK)
+               return retval;
        LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 
-       /* get flash size from target */
-       if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
+       /* get flash size from target. */
+       retval = target_read_u16(target, 0x1FFFF7E0, &num_pages);
+       if (retval != ERROR_OK)
        {
+               LOG_WARNING("failed reading flash size, default to max target family");
                /* failed reading flash size, default to max target family */
                num_pages = 0xffff;
        }
@@ -798,6 +938,36 @@ static int stm32x_probe(struct flash_bank *bank)
                        num_pages = 128;
                }
        }
+       else if ((device_id & 0x7ff) == 0x430)
+       {
+               /* xl line density - we have 2k pages
+                * 2 pages for a protection area */
+               page_size = 2048;
+               stm32x_info->ppage_size = 2;
+               stm32x_info->has_dual_banks = true;
+
+               /* check for early silicon */
+               if (num_pages == 0xffff)
+               {
+                       /* number of sectors may be incorrrect on early silicon */
+                       LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
+                       num_pages = 1024;
+               }
+
+               /* split reported size into matching bank */
+               if (bank->base != 0x08080000)
+               {
+                       /* bank 0 will be fixed 512k */
+                       num_pages = 512;
+               }
+               else
+               {
+                       num_pages -= 512;
+                       /* bank1 also uses a register offset */
+                       stm32x_info->register_offset = FLASH_OFFSET_B1;
+                       base_address = 0x08080000;
+               }
+       }
        else
        {
                LOG_WARNING("Cannot identify target as a STM32 family.");
@@ -815,7 +985,7 @@ static int stm32x_probe(struct flash_bank *bank)
                bank->sectors = NULL;
        }
 
-       bank->base = 0x08000000;
+       bank->base = base_address;
        bank->size = (num_pages * page_size);
        bank->num_sectors = num_pages;
        bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
@@ -855,7 +1025,9 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
        int printed;
 
        /* read stm32 device id register */
-       target_read_u32(target, 0xE0042000, &device_id);
+       int retval = target_read_u32(target, 0xE0042000, &device_id);
+       if (retval != ERROR_OK)
+               return retval;
 
        if ((device_id & 0x7ff) == 0x410)
        {
@@ -966,6 +1138,23 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
                                break;
                }
        }
+       else if ((device_id & 0x7ff) == 0x430)
+       {
+               printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
+               buf += printed;
+               buf_size -= printed;
+
+               switch (device_id >> 16)
+               {
+                       case 0x1000:
+                               snprintf(buf, buf_size, "A");
+                               break;
+
+                       default:
+                               snprintf(buf, buf_size, "unknown");
+                               break;
+               }
+       }
        else
        {
                snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
@@ -1001,6 +1190,10 @@ COMMAND_HANDLER(stm32x_handle_lock_command)
                return ERROR_TARGET_NOT_HALTED;
        }
 
+       retval = stm32x_check_operation_supported(bank);
+       if (ERROR_OK != retval)
+               return retval;
+
        if (stm32x_erase_options(bank) != ERROR_OK)
        {
                command_print(CMD_CTX, "stm32x failed to erase options");
@@ -1047,6 +1240,10 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
                return ERROR_TARGET_NOT_HALTED;
        }
 
+       retval = stm32x_check_operation_supported(bank);
+       if (ERROR_OK != retval)
+               return retval;
+
        if (stm32x_erase_options(bank) != ERROR_OK)
        {
                command_print(CMD_CTX, "stm32x failed to unlock device");
@@ -1093,7 +1290,13 @@ COMMAND_HANDLER(stm32x_handle_options_read_command)
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
+       retval = stm32x_check_operation_supported(bank);
+       if (ERROR_OK != retval)
+               return retval;
+
+       retval = target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
+       if (retval != ERROR_OK)
+               return retval;
        command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
 
        if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
@@ -1119,6 +1322,14 @@ COMMAND_HANDLER(stm32x_handle_options_read_command)
        else
                command_print(CMD_CTX, "Standby: Reset generated");
 
+       if (stm32x_info->has_dual_banks)
+       {
+               if (buf_get_u32((uint8_t*)&optionbyte, OPT_BFB2, 1))
+                       command_print(CMD_CTX, "Boot: Bank 0");
+               else
+                       command_print(CMD_CTX, "Boot: Bank 1");
+       }
+
        return ERROR_OK;
 }
 
@@ -1130,7 +1341,8 @@ COMMAND_HANDLER(stm32x_handle_options_write_command)
 
        if (CMD_ARGC < 4)
        {
-               command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
+               command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> "
+                               "<RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP> <BOOT0 | BOOT1>");
                return ERROR_OK;
        }
 
@@ -1149,6 +1361,10 @@ COMMAND_HANDLER(stm32x_handle_options_write_command)
                return ERROR_TARGET_NOT_HALTED;
        }
 
+       retval = stm32x_check_operation_supported(bank);
+       if (ERROR_OK != retval)
+               return retval;
+
        /* REVISIT: ignores some options which we will display...
         * and doesn't insist on the specified syntax.
         */
@@ -1163,8 +1379,8 @@ COMMAND_HANDLER(stm32x_handle_options_write_command)
                optionbyte &= ~(1 << 0);
        }
 
-       /* OPT_RDRSTSTDBY */
-       if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
+       /* OPT_RDRSTSTOP */
+       if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
        {
                optionbyte |= (1 << 1);
        }
@@ -1173,8 +1389,8 @@ COMMAND_HANDLER(stm32x_handle_options_write_command)
                optionbyte &= ~(1 << 1);
        }
 
-       /* OPT_RDRSTSTOP */
-       if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
+       /* OPT_RDRSTSTDBY */
+       if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
        {
                optionbyte |= (1 << 2);
        }
@@ -1183,6 +1399,19 @@ COMMAND_HANDLER(stm32x_handle_options_write_command)
                optionbyte &= ~(1 << 2);
        }
 
+       if (CMD_ARGC > 4 && stm32x_info->has_dual_banks)
+       {
+               /* OPT_BFB2 */
+               if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
+               {
+                       optionbyte |= (1 << 3);
+               }
+               else
+               {
+                       optionbyte &= ~(1 << 3);
+               }
+       }
+
        if (stm32x_erase_options(bank) != ERROR_OK)
        {
                command_print(CMD_CTX, "stm32x failed to erase options");
@@ -1215,18 +1444,18 @@ static int stm32x_mass_erase(struct flash_bank *bank)
        }
 
        /* unlock option flash registers */
-       int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
+       int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
        if (retval != ERROR_OK)
                return retval;
-       retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
+       retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
        if (retval != ERROR_OK)
                return retval;
 
        /* mass erase flash memory */
-       retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
+       retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
        if (retval != ERROR_OK)
                return retval;
-       retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
+       retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER | FLASH_STRT);
        if (retval != ERROR_OK)
                return retval;
 
@@ -1234,7 +1463,7 @@ static int stm32x_mass_erase(struct flash_bank *bank)
        if (retval != ERROR_OK)
                return retval;
 
-       retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
+       retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
        if (retval != ERROR_OK)
                return retval;
 
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)