NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010),
NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014),
- NRF5_FICR_CLENR0 = NRF5_FICR_REG(0x028),
- NRF5_FICR_PPFC = NRF5_FICR_REG(0x02C),
- NRF5_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
- NRF5_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
- NRF5_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
- NRF5_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
- NRF5_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
+
+ NRF51_FICR_CLENR0 = NRF5_FICR_REG(0x028),
+ NRF51_FICR_PPFC = NRF5_FICR_REG(0x02C),
+ NRF51_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
+ NRF51_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
+ NRF51_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
+ NRF51_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
+ NRF51_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
+
NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060),
NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064),
NRF5_FICR_DEVICEADDRTYPE = NRF5_FICR_REG(0x0A0),
NRF5_FICR_DEVICEADDR0 = NRF5_FICR_REG(0x0A4),
NRF5_FICR_DEVICEADDR1 = NRF5_FICR_REG(0x0A8),
- NRF5_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
- NRF5_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
- NRF5_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
- NRF5_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
- NRF5_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
- NRF5_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
- NRF5_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
- NRF5_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
- NRF5_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
- NRF5_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
- NRF5_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),
+
+ NRF51_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
+ NRF51_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
+ NRF51_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
+ NRF51_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
+ NRF51_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
+ NRF51_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
+ NRF51_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
+ NRF51_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
+ NRF51_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
+ NRF51_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
+ NRF51_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),
/* Following registers are available on nRF52 and on nRF51 since rev 3 */
NRF5_FICR_INFO_PART = NRF5_FICR_REG(0x100),
#define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
- NRF5_UICR_CLENR0 = NRF5_UICR_REG(0x000),
- NRF5_UICR_RBPCONF = NRF5_UICR_REG(0x004),
- NRF5_UICR_XTALFREQ = NRF5_UICR_REG(0x008),
- NRF5_UICR_FWID = NRF5_UICR_REG(0x010),
+ NRF51_UICR_CLENR0 = NRF5_UICR_REG(0x000),
+ NRF51_UICR_RBPCONF = NRF5_UICR_REG(0x004),
+ NRF51_UICR_XTALFREQ = NRF5_UICR_REG(0x008),
+ NRF51_UICR_FWID = NRF5_UICR_REG(0x010),
};
enum nrf5_nvmc_registers {
NRF5_NVMC_ERASEPAGE = NRF5_NVMC_REG(0x508),
NRF5_NVMC_ERASEALL = NRF5_NVMC_REG(0x50C),
NRF5_NVMC_ERASEUICR = NRF5_NVMC_REG(0x514),
+
+ NRF5_BPROT_BASE = 0x40000000,
};
enum nrf5_nvmc_config_bits {
uint32_t flash;
};
+enum nrf5_features {
+ NRF5_FEATURE_SERIES_51 = 1 << 0,
+ NRF5_FEATURE_SERIES_52 = 1 << 1,
+ NRF5_FEATURE_BPROT = 1 << 2,
+ NRF5_FEATURE_ACL_PROT = 1 << 3,
+};
+
struct nrf5_device_spec {
uint16_t hwid;
const char *part;
const char *variant;
const char *build_code;
unsigned int flash_size_kb;
+ enum nrf5_features features;
};
struct nrf5_info {
struct nrf52_ficr_info ficr_info;
const struct nrf5_device_spec *spec;
uint32_t hwid;
+ enum nrf5_features features;
unsigned int flash_size_kb;
+ unsigned int ram_size_kb;
};
-#define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize) \
+#define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
+{ \
+.hwid = (id), \
+.part = pt, \
+.variant = var, \
+.build_code = bcode, \
+.flash_size_kb = (fsize), \
+.features = NRF5_FEATURE_SERIES_51, \
+}
+
+#define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize, features) \
{ \
.hwid = (id), \
.part = pt, \
.variant = var, \
.build_code = bcode, \
.flash_size_kb = (fsize), \
+.features = features, \
}
/* The known devices table below is derived from the "nRF5x series
*/
static const struct nrf5_device_spec nrf5_known_devices_table[] = {
/* nRF51822 Devices (IC rev 1). */
- NRF5_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
- NRF5_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
- NRF5_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
- NRF5_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
- NRF5_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
+ NRF51_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
+ NRF51_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
+ NRF51_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
+ NRF51_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
+ NRF51_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
/* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
with built-in jlink seem to use engineering samples not listed
in the nRF51 Series Compatibility Matrix V1.0. */
- NRF5_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
+ NRF51_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
/* nRF51822 Devices (IC rev 2). */
- NRF5_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
- NRF5_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
- NRF5_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
- NRF5_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
- NRF5_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
- NRF5_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
- NRF5_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
- NRF5_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
- NRF5_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
+ NRF51_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
+ NRF51_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
+ NRF51_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
+ NRF51_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
+ NRF51_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
+ NRF51_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
+ NRF51_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
+ NRF51_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
+ NRF51_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
/* nRF51822 Devices (IC rev 3). */
- NRF5_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
- NRF5_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
- NRF5_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
- NRF5_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
- NRF5_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
- NRF5_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
- NRF5_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
- NRF5_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
- NRF5_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
+ NRF51_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
+ NRF51_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
+ NRF51_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
+ NRF51_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
+ NRF51_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
+ NRF51_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
+ NRF51_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
+ NRF51_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
+ NRF51_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
/* nRF51422 Devices (IC rev 1). */
- NRF5_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
- NRF5_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
- NRF5_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
+ NRF51_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
+ NRF51_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
+ NRF51_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
/* nRF51422 Devices (IC rev 2). */
- NRF5_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
- NRF5_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
- NRF5_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
- NRF5_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
+ NRF51_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
+ NRF51_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
+ NRF51_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
+ NRF51_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
/* nRF51422 Devices (IC rev 3). */
- NRF5_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
- NRF5_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
- NRF5_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
- NRF5_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
- NRF5_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
- NRF5_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
- NRF5_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
+ NRF51_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
+ NRF51_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
+ NRF51_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
+ NRF51_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
+ NRF51_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
+ NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
+ NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
/* The driver fully autodects nRF52 series devices by FICR INFO,
* no need for nRF52xxx HWIDs in this table */
#if 0
/* nRF52810 Devices */
- NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0", 192),
- NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0", 192),
+ NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
+ NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
/* nRF52832 Devices */
- NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512),
- NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512),
- NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512),
+ NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
+ NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
+ NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
/* nRF52840 Devices */
- NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024),
+ NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_ACL_PROT),
#endif
};
{ 0x2005, "CK" },
};
+const struct flash_driver nrf5_flash, nrf51_flash;
+
static int nrf5_bank_is_probed(struct flash_bank *bank)
{
struct nrf5_bank *nbank = bank->driver_priv;
return ERROR_FAIL;
}
+static int nrf5_protect_check_bprot(struct flash_bank *bank)
+{
+ struct nrf5_bank *nbank = bank->driver_priv;
+ struct nrf5_info *chip = nbank->chip;
+
+ assert(chip != NULL);
+
+ static uint32_t nrf5_bprot_offsets[4] = { 0x600, 0x604, 0x610, 0x614 };
+ uint32_t bprot_reg = 0;
+ int res;
+
+ for (int i = 0; i < bank->num_sectors; i++) {
+ unsigned int bit = i % 32;
+ if (bit == 0) {
+ unsigned int n_reg = i / 32;
+ if (n_reg >= ARRAY_SIZE(nrf5_bprot_offsets))
+ break;
+
+ res = target_read_u32(chip->target, NRF5_BPROT_BASE + nrf5_bprot_offsets[n_reg], &bprot_reg);
+ if (res != ERROR_OK)
+ return res;
+ }
+ bank->sectors[i].is_protected = (bprot_reg & (1 << bit)) ? 1 : 0;
+ }
+ return ERROR_OK;
+}
+
static int nrf5_protect_check(struct flash_bank *bank)
{
int res;
assert(chip != NULL);
- res = target_read_u32(chip->target, NRF5_FICR_CLENR0,
+ if (chip->features & NRF5_FEATURE_BPROT)
+ return nrf5_protect_check_bprot(bank);
+
+ if (!(chip->features & NRF5_FEATURE_SERIES_51)) {
+ LOG_WARNING("Flash protection of this nRF device is not supported");
+ return ERROR_FLASH_OPER_UNSUPPORTED;
+ }
+
+ res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
&clenr0);
if (res != ERROR_OK) {
LOG_ERROR("Couldn't read code region 0 size[FICR]");
}
if (clenr0 == 0xFFFFFFFF) {
- res = target_read_u32(chip->target, NRF5_UICR_CLENR0,
+ res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
&clenr0);
if (res != ERROR_OK) {
LOG_ERROR("Couldn't read code region 0 size[UICR]");
if (res != ERROR_OK)
return res;
+ if (!(chip->features & NRF5_FEATURE_SERIES_51)) {
+ LOG_ERROR("Flash protection setting of this nRF device is not supported");
+ return ERROR_FLASH_OPER_UNSUPPORTED;
+ }
+
if (first != 0) {
LOG_ERROR("Code region 0 must start at the begining of the bank");
return ERROR_FAIL;
}
- res = target_read_u32(chip->target, NRF5_FICR_PPFC,
+ res = target_read_u32(chip->target, NRF51_FICR_PPFC,
&ppfc);
if (res != ERROR_OK) {
LOG_ERROR("Couldn't read PPFC register");
return ERROR_FAIL;
}
- res = target_read_u32(chip->target, NRF5_UICR_CLENR0,
+ res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
&clenr0);
if (res != ERROR_OK) {
LOG_ERROR("Couldn't read code region 0 size[UICR]");
}
if (clenr0 == 0xFFFFFFFF) {
- res = target_write_u32(chip->target, NRF5_UICR_CLENR0,
+ res = target_write_u32(chip->target, NRF51_UICR_CLENR0,
clenr0);
if (res != ERROR_OK) {
LOG_ERROR("Couldn't write code region 0 size[UICR]");
{
struct nrf5_bank *nbank = bank->driver_priv;
struct nrf5_info *chip = nbank->chip;
+ int res;
if (chip->spec) {
- snprintf(buf, buf_size,
- "nRF%s-%s(build code: %s) %ukB Flash",
- chip->spec->part, chip->spec->variant, chip->spec->build_code,
- chip->flash_size_kb);
+ res = snprintf(buf, buf_size,
+ "nRF%s-%s(build code: %s)",
+ chip->spec->part, chip->spec->variant, chip->spec->build_code);
} else if (chip->ficr_info_valid) {
char variant[5];
nrf5_info_variant_to_str(chip->ficr_info.variant, variant);
- snprintf(buf, buf_size,
- "nRF%" PRIx32 "-%s%.2s(build code: %s) %" PRIu32
- "kB Flash, %" PRIu32 "kB RAM",
+ res = snprintf(buf, buf_size,
+ "nRF%" PRIx32 "-%s%.2s(build code: %s)",
chip->ficr_info.part,
nrf5_decode_info_package(chip->ficr_info.package),
- variant, &variant[2],
- chip->flash_size_kb,
- chip->ficr_info.ram);
+ variant, &variant[2]);
} else {
- snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ") %ukB Flash",
- chip->hwid, chip->flash_size_kb);
+ res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ")",
+ chip->hwid);
}
+ if (res <= 0)
+ return ERROR_FAIL;
+
+ snprintf(buf + res, buf_size - res, " %ukB Flash, %ukB RAM",
+ chip->flash_size_kb, chip->ram_size_kb);
return ERROR_OK;
}
}
uint32_t series = chip->ficr_info.part & 0xfffff000;
- if (!(series == 0x51000 || series == 0x52000)) {
+ switch (series) {
+ case 0x51000:
+ chip->features = NRF5_FEATURE_SERIES_51;
+ break;
+
+ case 0x52000:
+ chip->features = NRF5_FEATURE_SERIES_52;
+
+ switch (chip->ficr_info.part) {
+ case 0x52810:
+ case 0x52832:
+ chip->features |= NRF5_FEATURE_BPROT;
+ break;
+
+ case 0x52840:
+ chip->features |= NRF5_FEATURE_ACL_PROT;
+ break;
+ }
+ break;
+
+ default:
LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
PRIx32, chip->ficr_info.part);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
return ERROR_OK;
}
+static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size)
+{
+ int res;
+
+ *ram_size = 0;
+
+ uint32_t numramblock;
+ res = target_read_u32(target, NRF51_FICR_NUMRAMBLOCK, &numramblock);
+ if (res != ERROR_OK) {
+ LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
+ return res;
+ }
+
+ if (numramblock < 1 || numramblock > 4) {
+ LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32, numramblock);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ for (unsigned int i = 0; i < numramblock; i++) {
+ uint32_t sizeramblock;
+ res = target_read_u32(target, NRF51_FICR_SIZERAMBLOCK0 + sizeof(uint32_t)*i, &sizeramblock);
+ if (res != ERROR_OK) {
+ LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
+ return res;
+ }
+ if (sizeramblock < 1024 || sizeramblock > 65536)
+ LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32, sizeramblock);
+ else
+ *ram_size += sizeramblock;
+ }
+ return res;
+}
+
static int nrf5_probe(struct flash_bank *bank)
{
int res;
chip->hwid &= 0xFFFF; /* HWID is stored in the lower two
* bytes of the CONFIGID register */
+ /* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
+ chip->features = NRF5_FEATURE_SERIES_51;
+
+ /* Don't bail out on error for the case that some old engineering
+ * sample has FICR INFO registers unreadable. We can proceed anyway. */
+ (void)nrf5_read_ficr_info(chip);
+
chip->spec = NULL;
for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
if (chip->hwid == nrf5_known_devices_table[i].hwid) {
chip->spec = &nrf5_known_devices_table[i];
+ chip->features = chip->spec->features;
break;
}
}
- /* Don't bail out on error for the case that some old engineering
- * sample has FICR INFO registers unreadable. We can proceed anyway. */
- (void)nrf5_read_ficr_info(chip);
-
if (chip->spec && chip->ficr_info_valid) {
/* check if HWID table gives the same part as FICR INFO */
if (chip->ficr_info.part != strtoul(chip->spec->part, NULL, 16))
PRIx32, chip->hwid, chip->ficr_info.part);
}
+ if (chip->ficr_info_valid) {
+ chip->ram_size_kb = chip->ficr_info.ram;
+ } else {
+ uint32_t ram_size;
+ nrf5_get_ram_size(target, &ram_size);
+ chip->ram_size_kb = ram_size / 1024;
+ }
+
/* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
uint32_t flash_page_size;
res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE,
}
}
+ free(bank->sectors);
if (bank->base == NRF5_FLASH_BASE) {
- bank->num_sectors = num_sectors;
- bank->size = num_sectors * flash_page_size;
-
/* Sanity check */
if (chip->spec && chip->flash_size_kb != chip->spec->flash_size_kb)
LOG_WARNING("Chip's reported Flash capacity does not match expected one");
if (chip->ficr_info_valid && chip->flash_size_kb != chip->ficr_info.flash)
LOG_WARNING("Chip's reported Flash capacity does not match FICR INFO.FLASH");
- bank->sectors = calloc(bank->num_sectors,
- sizeof((bank->sectors)[0]));
- if (!bank->sectors)
- return ERROR_FLASH_BANK_NOT_PROBED;
-
- /* Fill out the sector information: all NRF5 sectors are the same size and
- * there is always a fixed number of them. */
- for (int i = 0; i < bank->num_sectors; i++) {
- bank->sectors[i].size = flash_page_size;
- bank->sectors[i].offset = i * flash_page_size;
+ bank->num_sectors = num_sectors;
+ bank->size = num_sectors * flash_page_size;
- /* mark as unknown */
- bank->sectors[i].is_erased = -1;
- bank->sectors[i].is_protected = -1;
- }
+ bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
+ if (!bank->sectors)
+ return ERROR_FAIL;
nrf5_protect_check(bank);
chip->bank[0].probed = true;
+
} else {
- bank->size = flash_page_size;
bank->num_sectors = 1;
- bank->sectors = calloc(bank->num_sectors,
- sizeof((bank->sectors)[0]));
- if (!bank->sectors)
- return ERROR_FLASH_BANK_NOT_PROBED;
+ bank->size = flash_page_size;
- bank->sectors[0].size = bank->size;
- bank->sectors[0].offset = 0;
+ bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
+ if (!bank->sectors)
+ return ERROR_FAIL;
- bank->sectors[0].is_erased = 0;
bank->sectors[0].is_protected = 0;
chip->bank[1].probed = true;
int res;
LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
- if (sector->is_protected) {
- LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
- return ERROR_FAIL;
- }
if (bank->base == NRF5_UICR_BASE) {
- uint32_t ppfc;
- res = target_read_u32(chip->target, NRF5_FICR_PPFC,
+ if (chip->features & NRF5_FEATURE_SERIES_51) {
+ uint32_t ppfc;
+ res = target_read_u32(chip->target, NRF51_FICR_PPFC,
&ppfc);
- if (res != ERROR_OK) {
- LOG_ERROR("Couldn't read PPFC register");
- return res;
- }
-
- if ((ppfc & 0xFF) == 0xFF) {
- /* We can't erase the UICR. Double-check to
- see if it's already erased before complaining. */
- default_flash_blank_check(bank);
- if (sector->is_erased == 1)
- return ERROR_OK;
-
- LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
- return ERROR_FAIL;
+ if (res != ERROR_OK) {
+ LOG_ERROR("Couldn't read PPFC register");
+ return res;
+ }
+
+ if ((ppfc & 0xFF) == 0xFF) {
+ /* We can't erase the UICR. Double-check to
+ see if it's already erased before complaining. */
+ default_flash_blank_check(bank);
+ if (sector->is_erased == 1)
+ return ERROR_OK;
+
+ LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
+ return ERROR_FAIL;
+ }
}
res = nrf5_nvmc_generic_erase(chip,
}
}
+static struct nrf5_info *nrf5_get_chip(struct target *target)
+{
+ struct flash_bank *bank_iter;
+
+ /* iterate over nrf5 banks of same target */
+ for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
+ if (bank_iter->driver != &nrf5_flash && bank_iter->driver != &nrf51_flash)
+ continue;
+
+ if (bank_iter->target != target)
+ continue;
+
+ struct nrf5_bank *nbank = bank_iter->driver_priv;
+ if (!nbank)
+ continue;
+
+ if (nbank->chip)
+ return nbank->chip;
+ }
+ return NULL;
+}
+
FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
{
- static struct nrf5_info *chip;
+ struct nrf5_info *chip;
struct nrf5_bank *nbank = NULL;
switch (bank->base) {
return ERROR_FAIL;
}
+ chip = nrf5_get_chip(bank->target);
if (!chip) {
/* Create a new chip */
chip = calloc(1, sizeof(*chip));
if (res != ERROR_OK)
return res;
- uint32_t ppfc;
-
- res = target_read_u32(target, NRF5_FICR_PPFC,
+ if (chip->features & NRF5_FEATURE_SERIES_51) {
+ uint32_t ppfc;
+ res = target_read_u32(target, NRF51_FICR_PPFC,
&ppfc);
- if (res != ERROR_OK) {
- LOG_ERROR("Couldn't read PPFC register");
- return res;
- }
+ if (res != ERROR_OK) {
+ LOG_ERROR("Couldn't read PPFC register");
+ return res;
+ }
- if ((ppfc & 0xFF) == 0x00) {
- LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
- "mass erase command won't work.");
- return ERROR_FAIL;
+ if ((ppfc & 0xFF) == 0x00) {
+ LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
+ "mass erase command won't work.");
+ return ERROR_FAIL;
+ }
}
res = nrf5_erase_all(chip);
} ficr[] = {
{ .address = NRF5_FICR_CODEPAGESIZE },
{ .address = NRF5_FICR_CODESIZE },
- { .address = NRF5_FICR_CLENR0 },
- { .address = NRF5_FICR_PPFC },
- { .address = NRF5_FICR_NUMRAMBLOCK },
- { .address = NRF5_FICR_SIZERAMBLOCK0 },
- { .address = NRF5_FICR_SIZERAMBLOCK1 },
- { .address = NRF5_FICR_SIZERAMBLOCK2 },
- { .address = NRF5_FICR_SIZERAMBLOCK3 },
+ { .address = NRF51_FICR_CLENR0 },
+ { .address = NRF51_FICR_PPFC },
+ { .address = NRF51_FICR_NUMRAMBLOCK },
+ { .address = NRF51_FICR_SIZERAMBLOCK0 },
+ { .address = NRF51_FICR_SIZERAMBLOCK1 },
+ { .address = NRF51_FICR_SIZERAMBLOCK2 },
+ { .address = NRF51_FICR_SIZERAMBLOCK3 },
{ .address = NRF5_FICR_CONFIGID },
{ .address = NRF5_FICR_DEVICEID0 },
{ .address = NRF5_FICR_DEVICEID1 },
{ .address = NRF5_FICR_DEVICEADDRTYPE },
{ .address = NRF5_FICR_DEVICEADDR0 },
{ .address = NRF5_FICR_DEVICEADDR1 },
- { .address = NRF5_FICR_OVERRIDEN },
- { .address = NRF5_FICR_NRF_1MBIT0 },
- { .address = NRF5_FICR_NRF_1MBIT1 },
- { .address = NRF5_FICR_NRF_1MBIT2 },
- { .address = NRF5_FICR_NRF_1MBIT3 },
- { .address = NRF5_FICR_NRF_1MBIT4 },
- { .address = NRF5_FICR_BLE_1MBIT0 },
- { .address = NRF5_FICR_BLE_1MBIT1 },
- { .address = NRF5_FICR_BLE_1MBIT2 },
- { .address = NRF5_FICR_BLE_1MBIT3 },
- { .address = NRF5_FICR_BLE_1MBIT4 },
+ { .address = NRF51_FICR_OVERRIDEN },
+ { .address = NRF51_FICR_NRF_1MBIT0 },
+ { .address = NRF51_FICR_NRF_1MBIT1 },
+ { .address = NRF51_FICR_NRF_1MBIT2 },
+ { .address = NRF51_FICR_NRF_1MBIT3 },
+ { .address = NRF51_FICR_NRF_1MBIT4 },
+ { .address = NRF51_FICR_BLE_1MBIT0 },
+ { .address = NRF51_FICR_BLE_1MBIT1 },
+ { .address = NRF51_FICR_BLE_1MBIT2 },
+ { .address = NRF51_FICR_BLE_1MBIT3 },
+ { .address = NRF51_FICR_BLE_1MBIT4 },
}, uicr[] = {
- { .address = NRF5_UICR_CLENR0, },
- { .address = NRF5_UICR_RBPCONF },
- { .address = NRF5_UICR_XTALFREQ },
- { .address = NRF5_UICR_FWID },
+ { .address = NRF51_UICR_CLENR0, },
+ { .address = NRF51_UICR_RBPCONF },
+ { .address = NRF51_UICR_XTALFREQ },
+ { .address = NRF51_UICR_FWID },
};
for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
Code Review / openocd.git / blobdiff