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flash/nor: Use proper data types in driver API
[openocd.git] / src / flash / nor / nrf5.c
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index c19c4eabb05f741867f6928ef36b736737b9fa6d..a79aa78b907cfb8f5955e06abddd26d467d2d2e4 100644 (file)
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -28,6 +28,10 @@
 #include <helper/types.h>
 #include <helper/time_support.h>
 
+/* Both those values are constant across the current spectrum ofr nRF5 devices */
+#define WATCHDOG_REFRESH_REGISTER       0x40010600
+#define WATCHDOG_REFRESH_VALUE          0x6e524635
+
 enum {
        NRF5_FLASH_BASE = 0x00000000,
 };
@@ -157,6 +161,7 @@ struct nrf5_info {
        uint32_t hwid;
        enum nrf5_features features;
        unsigned int flash_size_kb;
+       unsigned int ram_size_kb;
 };
 
 #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
@@ -282,6 +287,8 @@ static const struct nrf5_device_package nrf5_packages_table[] = {
        { 0x2005, "CK" },
 };
 
+const struct flash_driver nrf5_flash, nrf51_flash;
+
 static int nrf5_bank_is_probed(struct flash_bank *bank)
 {
        struct nrf5_bank *nbank = bank->driver_priv;
@@ -444,7 +451,7 @@ static int nrf5_protect_check_bprot(struct flash_bank *bank)
        uint32_t bprot_reg = 0;
        int res;
 
-       for (int i = 0; i < bank->num_sectors; i++) {
+       for (unsigned int i = 0; i < bank->num_sectors; i++) {
                unsigned int bit = i % 32;
                if (bit == 0) {
                        unsigned int n_reg = i / 32;
@@ -498,14 +505,15 @@ static int nrf5_protect_check(struct flash_bank *bank)
                }
        }
 
-       for (int i = 0; i < bank->num_sectors; i++)
+       for (unsigned int i = 0; i < bank->num_sectors; i++)
                bank->sectors[i].is_protected =
                        clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
 
        return ERROR_OK;
 }
 
-static int nrf5_protect(struct flash_bank *bank, int set, int first, int last)
+static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
+               unsigned int last)
 {
        int res;
        uint32_t clenr0, ppfc;
@@ -567,10 +575,14 @@ static int nrf5_protect(struct flash_bank *bank, int set, int first, int last)
 
 static bool nrf5_info_variant_to_str(uint32_t variant, char *bf)
 {
-       h_u32_to_be((uint8_t *)bf, variant);
-       bf[4] = '\0';
-       if (isalnum(bf[0]) && isalnum(bf[1]) && isalnum(bf[2]) && isalnum(bf[3]))
+       uint8_t b[4];
+
+       h_u32_to_be(b, variant);
+       if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) && isalnum(b[3])) {
+               memcpy(bf, b, 4);
+               bf[4] = 0;
                return true;
+       }
 
        strcpy(bf, "xxxx");
        return false;
@@ -589,29 +601,31 @@ static int nrf5_info(struct flash_bank *bank, char *buf, int buf_size)
 {
        struct nrf5_bank *nbank = bank->driver_priv;
        struct nrf5_info *chip = nbank->chip;
+       int res;
 
        if (chip->spec) {
-               snprintf(buf, buf_size,
-                               "nRF%s-%s(build code: %s) %ukB Flash",
-                               chip->spec->part, chip->spec->variant, chip->spec->build_code,
-                               chip->flash_size_kb);
+               res = snprintf(buf, buf_size,
+                               "nRF%s-%s(build code: %s)",
+                               chip->spec->part, chip->spec->variant, chip->spec->build_code);
 
        } else if (chip->ficr_info_valid) {
                char variant[5];
                nrf5_info_variant_to_str(chip->ficr_info.variant, variant);
-               snprintf(buf, buf_size,
-                               "nRF%" PRIx32 "-%s%.2s(build code: %s) %" PRIu32
-                               "kB Flash, %" PRIu32 "kB RAM",
+               res = snprintf(buf, buf_size,
+                               "nRF%" PRIx32 "-%s%.2s(build code: %s)",
                                chip->ficr_info.part,
                                nrf5_decode_info_package(chip->ficr_info.package),
-                               variant, &variant[2],
-                               chip->flash_size_kb,
-                               chip->ficr_info.ram);
+                               variant, &variant[2]);
 
        } else {
-               snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ") %ukB Flash",
-                               chip->hwid, chip->flash_size_kb);
+               res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%08" PRIx32 ")",
+                               chip->hwid);
        }
+       if (res <= 0)
+               return ERROR_FAIL;
+
+       snprintf(buf + res, buf_size - res, " %ukB Flash, %ukB RAM",
+                               chip->flash_size_kb, chip->ram_size_kb);
        return ERROR_OK;
 }
 
@@ -681,6 +695,39 @@ static int nrf5_read_ficr_info(struct nrf5_info *chip)
        return ERROR_OK;
 }
 
+static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size)
+{
+       int res;
+
+       *ram_size = 0;
+
+       uint32_t numramblock;
+       res = target_read_u32(target, NRF51_FICR_NUMRAMBLOCK, &numramblock);
+       if (res != ERROR_OK) {
+               LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
+               return res;
+       }
+
+       if (numramblock < 1 || numramblock > 4) {
+               LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32, numramblock);
+               return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+       }
+
+       for (unsigned int i = 0; i < numramblock; i++) {
+               uint32_t sizeramblock;
+               res = target_read_u32(target, NRF51_FICR_SIZERAMBLOCK0 + sizeof(uint32_t)*i, &sizeramblock);
+               if (res != ERROR_OK) {
+                       LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
+                       return res;
+               }
+               if (sizeramblock < 1024 || sizeramblock > 65536)
+                       LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32, sizeramblock);
+               else
+                       *ram_size += sizeramblock;
+       }
+       return res;
+}
+
 static int nrf5_probe(struct flash_bank *bank)
 {
        int res;
@@ -720,6 +767,14 @@ static int nrf5_probe(struct flash_bank *bank)
                                                PRIx32, chip->hwid, chip->ficr_info.part);
        }
 
+       if (chip->ficr_info_valid) {
+               chip->ram_size_kb = chip->ficr_info.ram;
+       } else {
+               uint32_t ram_size;
+               nrf5_get_ram_size(target, &ram_size);
+               chip->ram_size_kb = ram_size / 1024;
+       }
+
        /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
        uint32_t flash_page_size;
        res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE,
@@ -750,6 +805,8 @@ static int nrf5_probe(struct flash_bank *bank)
                }
        }
 
+       free(bank->sectors);
+
        if (bank->base == NRF5_FLASH_BASE) {
                /* Sanity check */
                if (chip->spec && chip->flash_size_kb != chip->spec->flash_size_kb)
@@ -811,10 +868,6 @@ static int nrf5_erase_page(struct flash_bank *bank,
        int res;
 
        LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
-       if (sector->is_protected) {
-               LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
-               return ERROR_FAIL;
-       }
 
        if (bank->base == NRF5_UICR_BASE) {
                if (chip->features & NRF5_FEATURE_SERIES_51) {
@@ -852,30 +905,6 @@ static int nrf5_erase_page(struct flash_bank *bank,
        return res;
 }
 
-static const uint8_t nrf5_flash_write_code[] = {
-       /* See contrib/loaders/flash/cortex-m0.S */
-/* <wait_fifo>: */
-       0x0d, 0x68,             /* ldr  r5,     [r1,    #0] */
-       0x00, 0x2d,             /* cmp  r5,     #0 */
-       0x0b, 0xd0,             /* beq.n        1e <exit> */
-       0x4c, 0x68,             /* ldr  r4,     [r1,    #4] */
-       0xac, 0x42,             /* cmp  r4,     r5 */
-       0xf9, 0xd0,             /* beq.n        0 <wait_fifo> */
-       0x20, 0xcc,             /* ldmia        r4!,    {r5} */
-       0x20, 0xc3,             /* stmia        r3!,    {r5} */
-       0x94, 0x42,             /* cmp  r4,     r2 */
-       0x01, 0xd3,             /* bcc.n        18 <no_wrap> */
-       0x0c, 0x46,             /* mov  r4,     r1 */
-       0x08, 0x34,             /* adds r4,     #8 */
-/* <no_wrap>: */
-       0x4c, 0x60,             /* str  r4, [r1,        #4] */
-       0x04, 0x38,             /* subs r0, #4 */
-       0xf0, 0xd1,             /* bne.n        0 <wait_fifo> */
-/* <exit>: */
-       0x00, 0xbe              /* bkpt 0x0000 */
-};
-
-
 /* Start a low level flash write for the specified region */
 static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const uint8_t *buffer, uint32_t bytes)
 {
@@ -883,10 +912,14 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u
        uint32_t buffer_size = 8192;
        struct working_area *write_algorithm;
        struct working_area *source;
-       struct reg_param reg_params[4];
+       struct reg_param reg_params[6];
        struct armv7m_algorithm armv7m_info;
        int retval = ERROR_OK;
 
+       static const uint8_t nrf5_flash_write_code[] = {
+#include "../../../contrib/loaders/flash/nrf5/nrf5.inc"
+       };
+
        LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32" bytes=0x%"PRIx32, address, bytes);
        assert(bytes % 4 == 0);
 
@@ -937,15 +970,19 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u
        init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* buffer start */
        init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer end */
        init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
+       init_reg_param(&reg_params[4], "r6", 32, PARAM_OUT);    /* watchdog refresh value */
+       init_reg_param(&reg_params[5], "r7", 32, PARAM_OUT);    /* watchdog refresh register address */
 
        buf_set_u32(reg_params[0].value, 0, 32, bytes);
        buf_set_u32(reg_params[1].value, 0, 32, source->address);
        buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
        buf_set_u32(reg_params[3].value, 0, 32, address);
+       buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE);
+       buf_set_u32(reg_params[5].value, 0, 32, WATCHDOG_REFRESH_REGISTER);
 
        retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
                        0, NULL,
-                       4, reg_params,
+                       ARRAY_SIZE(reg_params), reg_params,
                        source->address, source->size,
                        write_algorithm->address, 0,
                        &armv7m_info);
@@ -957,6 +994,8 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u
        destroy_reg_param(&reg_params[1]);
        destroy_reg_param(&reg_params[2]);
        destroy_reg_param(&reg_params[3]);
+       destroy_reg_param(&reg_params[4]);
+       destroy_reg_param(&reg_params[5]);
 
        return retval;
 }
@@ -989,7 +1028,8 @@ error:
        return res;
 }
 
-static int nrf5_erase(struct flash_bank *bank, int first, int last)
+static int nrf5_erase(struct flash_bank *bank, unsigned int first,
+               unsigned int last)
 {
        int res;
        struct nrf5_info *chip;
@@ -999,7 +1039,7 @@ static int nrf5_erase(struct flash_bank *bank, int first, int last)
                return res;
 
        /* For each sector to be erased */
-       for (int s = first; s <= last && res == ERROR_OK; s++)
+       for (unsigned int s = first; s <= last && res == ERROR_OK; s++)
                res = nrf5_erase_page(bank, chip, &bank->sectors[s]);
 
        return res;
@@ -1019,9 +1059,31 @@ static void nrf5_free_driver_priv(struct flash_bank *bank)
        }
 }
 
+static struct nrf5_info *nrf5_get_chip(struct target *target)
+{
+       struct flash_bank *bank_iter;
+
+       /* iterate over nrf5 banks of same target */
+       for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
+               if (bank_iter->driver != &nrf5_flash && bank_iter->driver != &nrf51_flash)
+                       continue;
+
+               if (bank_iter->target != target)
+                       continue;
+
+               struct nrf5_bank *nbank = bank_iter->driver_priv;
+               if (!nbank)
+                       continue;
+
+               if (nbank->chip)
+                       return nbank->chip;
+       }
+       return NULL;
+}
+
 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
 {
-       static struct nrf5_info *chip;
+       struct nrf5_info *chip;
        struct nrf5_bank *nbank = NULL;
 
        switch (bank->base) {
@@ -1033,6 +1095,7 @@ FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
                return ERROR_FAIL;
        }
 
+       chip = nrf5_get_chip(bank->target);
        if (!chip) {
                /* Create a new chip */
                chip = calloc(1, sizeof(*chip));
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