* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
/*
static const char target_not_halted_err_msg[] =
"target must be halted to use mx3 NAND flash controller";
static const char data_block_size_err_msg[] =
- "minimal granularity is one half-word, %" PRId32 " is incorrect";
+ "minimal granularity is one half-word, %" PRIu32 " is incorrect";
static const char sram_buffer_bounds_err_msg[] =
"trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
static const char get_status_register_err_msg[] = "can't get NAND status";
{
struct mx3_nf_controller *mx3_nf_info;
mx3_nf_info = malloc(sizeof(struct mx3_nf_controller));
- if (mx3_nf_info == NULL) {
+ if (!mx3_nf_info) {
LOG_ERROR("no memory for nand controller");
return ERROR_FAIL;
}
mx3_nf_info->fin = MX3_NF_FIN_NONE;
mx3_nf_info->flags.target_little_endian =
(nand->target->endianness == TARGET_LITTLE_ENDIAN);
- /*
- * testing host endianness
- */
- {
- int x = 1;
- if (*(char *) &x == 1)
- mx3_nf_info->flags.host_little_endian = 1;
- else
- mx3_nf_info->flags.host_little_endian = 0;
- }
+
return ERROR_OK;
}
uint32_t gpr_register_content;
target_read_u32(target, MX3_GPR, &gpr_register_content);
if (gpr_register_content & 0x00000060) {
- LOG_ERROR("pins mode overrided by GPR");
+ LOG_ERROR("pins mode overridden by GPR");
return ERROR_FAIL;
}
}
* offset == one half of page size
*/
in_sram_address = MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
+ break;
default:
in_sram_address = MX3_NF_MAIN_BUFFER0;
}
if (oob) {
if (mx3_nf_info->flags.hw_ecc_enabled) {
/*
- * part of spare block will be overrided by hardware
+ * part of spare block will be overridden by hardware
* ECC generator
*/
- LOG_DEBUG("part of spare block will be overrided by hardware ECC generator");
+ LOG_DEBUG("part of spare block will be overridden by hardware ECC generator");
}
target_write_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size, oob);
}
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
struct target *target = nand->target;
/*
- * resets NAND flash controller in zero time ? I dont know.
+ * resets NAND flash controller in zero time ? I don't know.
*/
target_write_u16(target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
{
target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
switch (ecc_status & 0x000c) {
case 1 << 2:
- LOG_DEBUG("main area readed with 1 (correctable) error");
+ LOG_DEBUG("main area read with 1 (correctable) error");
break;
case 2 << 2:
- LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
+ LOG_DEBUG("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
- break;
}
switch (ecc_status & 0x0003) {
case 1:
- LOG_DEBUG("spare area readed with 1 (correctable) error");
+ LOG_DEBUG("spare area read with 1 (correctable) error");
break;
case 2:
- LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
+ LOG_DEBUG("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
- break;
}
}
break;