* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
****************************************************************************/
-/***************************************************************************************************************************************************************************************
+/***************************************************************************
*
* New flash setup command:
*
-* flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
+* flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_id>
+* [<chip_type> <banks>
+* <sectors_per_bank> <pages_per_sector>
+* <page_size> <num_nvmbits>
+* <ext_freq_khz>]
*
* <ext_freq_khz> - MUST be used if clock is from external source,
-* CAN be used if main oscillator frequency is known (recomended)
+* CAN be used if main oscillator frequency is known (recommended)
* Examples:
-* flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 25000 ==== RECOMENDED ============
-* flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 25000 (auto-detection, except for clock) ==== RECOMENDED ============
-* flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 0 ==== NOT RECOMENDED !!! ====
-* flash bank at91sam7 0 0 0 0 0 (old style, full auto-detection) ==== NOT RECOMENDED !!! ====
-****************************************************************************************************************************************************************************************/
+* ==== RECOMMENDED (covers clock speed) ============
+* flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 25000
+* (if auto-detect fails; provides clock spec)
+* flash bank at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 25000
+* (auto-detect everything except the clock)
+* ==== NOT RECOMMENDED !!! (clock speed is not configured) ====
+* flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 0
+* (if auto-detect fails)
+* flash bank at91sam7 0 0 0 0 $_TARGETNAME
+* (old style, auto-detect everything)
+****************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
static uint32_t at91sam7_get_flash_status(target_t *target, int bank_number);
static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode);
static uint32_t at91sam7_wait_status_busy(flash_bank_t *bank, uint32_t waitbits, int timeout);
-static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen);
+static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen);
static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
flash_driver_t at91sam7_flash =
static long SRAMSIZ[16] = {
-1,
0x0400, /* 1K */
- 0x0800, /* 2K */
- -1,
+ 0x0800, /* 2K */
+ -1,
0x1c000, /* 112K */
0x1000, /* 4K */
0x14000, /* 80K */
command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL);
register_command(cmd_ctx, at91sam7_cmd, "gpnvm", at91sam7_handle_gpnvm_command, COMMAND_EXEC,
- "at91sam7 gpnvm <bit> set|clear, set or clear one gpnvm bit");
+ "at91sam7 gpnvm <bit> set | clear, set or clear one gpnvm bit");
return ERROR_OK;
}
target_read_u32(target, PMC_MCKR, &mckr);
/* Read Clock Generator PLL Register */
target_read_u32(target, CKGR_PLLR, &pllr);
-
+
at91sam7_info->mck_valid = 0;
at91sam7_info->mck_freq = 0;
- switch (mckr & PMC_MCKR_CSS)
+ switch (mckr & PMC_MCKR_CSS)
{
case 0: /* Slow Clock */
at91sam7_info->mck_valid = 1;
break;
case 1: /* Main Clock */
- if ((mcfr & CKGR_MCFR_MAINRDY) &&
+ if ((mcfr & CKGR_MCFR_MAINRDY) &&
(at91sam7_info->ext_freq == 0))
{
at91sam7_info->mck_valid = 1;
break;
case 3: /* PLL Clock */
- if ((mcfr & CKGR_MCFR_MAINRDY) &&
- (at91sam7_info->ext_freq == 0))
+ if ((mcfr & CKGR_MCFR_MAINRDY) &&
+ (at91sam7_info->ext_freq == 0))
{
target_read_u32(target, CKGR_PLLR, &pllr);
if (!(pllr & CKGR_PLLR_DIV))
}
/* Prescaler adjust */
- if ( (((mckr & PMC_MCKR_PRES) >> 2) == 7) || (tmp == 0) )
+ if ((((mckr & PMC_MCKR_PRES) >> 2) == 7) || (tmp == 0))
{
at91sam7_info->mck_valid = 0;
at91sam7_info->mck_freq = 0;
if (at91sam7_info->cidr_arch == 0x60)
{
/* AT91SAM7A3 uses master clocks in 100 ns */
- fmcn = (at91sam7_info->mck_freq/10000000ul)+1;
+ fmcn = (at91sam7_info->mck_freq/10000000ul) + 1;
}
else
{
/* master clocks in 1uS for ARCH 0x7 types */
- fmcn = (at91sam7_info->mck_freq/1000000ul)+1;
+ fmcn = (at91sam7_info->mck_freq/1000000ul) + 1;
}
}
else if (mode == FMR_TIMING_FLASH)
{
/* main clocks in 1.5uS */
fmcn = (at91sam7_info->mck_freq/1000000ul)+
- (at91sam7_info->mck_freq/2000000ul)+1;
+ (at91sam7_info->mck_freq/2000000ul) + 1;
}
/* hard overclocking */
if (fmcn > 0xFF)
fmcn = 0xFF;
- /* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */
+ /* Only allow fmcn = 0 if clock period is > 30 us = 33kHz. */
if (at91sam7_info->mck_freq <= 33333ul)
fmcn = 0;
- /* Only allow fws=0 if clock frequency is < 30 MHz. */
+ /* Only allow fws = 0 if clock frequency is < 30 MHz. */
if (at91sam7_info->mck_freq > 30000000ul)
fws = 1;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
- fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd;
+ fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
target_write_u32(target, MC_FCR[bank->bank_number], fcr);
- LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number+1, pagen);
+ LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number + 1, pagen);
- if ((at91sam7_info->cidr_arch == 0x60)&&((cmd==SLB)|(cmd==CLB)))
+ if ((at91sam7_info->cidr_arch == 0x60) && ((cmd == SLB) | (cmd == CLB)))
{
/* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
return ERROR_OK;
}
- if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
+ if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
{
return ERROR_FLASH_OPERATION_FAILED;
}
at91sam7_info = t_bank->driver_priv;
at91sam7_info->cidr = cidr;
- at91sam7_info->cidr_ext = (cidr>>31)&0x0001;
- at91sam7_info->cidr_nvptyp = (cidr>>28)&0x0007;
- at91sam7_info->cidr_arch = (cidr>>20)&0x00FF;
- at91sam7_info->cidr_sramsiz = (cidr>>16)&0x000F;
- at91sam7_info->cidr_nvpsiz2 = (cidr>>12)&0x000F;
- at91sam7_info->cidr_nvpsiz = (cidr>>8)&0x000F;
- at91sam7_info->cidr_eproc = (cidr>>5)&0x0007;
+ at91sam7_info->cidr_ext = (cidr >> 31)&0x0001;
+ at91sam7_info->cidr_nvptyp = (cidr >> 28)&0x0007;
+ at91sam7_info->cidr_arch = (cidr >> 20)&0x00FF;
+ at91sam7_info->cidr_sramsiz = (cidr >> 16)&0x000F;
+ at91sam7_info->cidr_nvpsiz2 = (cidr >> 12)&0x000F;
+ at91sam7_info->cidr_nvpsiz = (cidr >> 8)&0x000F;
+ at91sam7_info->cidr_eproc = (cidr >> 5)&0x0007;
at91sam7_info->cidr_version = cidr&0x001F;
/* calculate master clock frequency */
return ERROR_OK;
}
- arch = (cidr>>20)&0x00FF;
+ arch = (cidr >> 20)&0x00FF;
/* check flash size */
- switch ((cidr>>8)&0x000F)
+ switch ((cidr >> 8)&0x000F)
{
case FLASH_SIZE_8KB:
break;
/* calculate bank size */
bank_size = sectors_num * pages_per_sector * page_size;
- for (bnk=0; bnk<banks_num; bnk++)
+ for (bnk = 0; bnk < banks_num; bnk++)
{
if (bnk > 0)
{
/* allocate sectors */
t_bank->sectors = malloc(sectors_num * sizeof(flash_sector_t));
- for (sec=0; sec<sectors_num; sec++)
+ for (sec = 0; sec < sectors_num; sec++)
{
t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
t_bank->sectors[sec].size = pages_per_sector * page_size;
at91sam7_info = t_bank->driver_priv;
at91sam7_info->cidr = cidr;
- at91sam7_info->cidr_ext = (cidr>>31)&0x0001;
- at91sam7_info->cidr_nvptyp = (cidr>>28)&0x0007;
- at91sam7_info->cidr_arch = (cidr>>20)&0x00FF;
- at91sam7_info->cidr_sramsiz = (cidr>>16)&0x000F;
- at91sam7_info->cidr_nvpsiz2 = (cidr>>12)&0x000F;
- at91sam7_info->cidr_nvpsiz = (cidr>>8)&0x000F;
- at91sam7_info->cidr_eproc = (cidr>>5)&0x0007;
+ at91sam7_info->cidr_ext = (cidr >> 31)&0x0001;
+ at91sam7_info->cidr_nvptyp = (cidr >> 28)&0x0007;
+ at91sam7_info->cidr_arch = (cidr >> 20)&0x00FF;
+ at91sam7_info->cidr_sramsiz = (cidr >> 16)&0x000F;
+ at91sam7_info->cidr_nvpsiz2 = (cidr >> 12)&0x000F;
+ at91sam7_info->cidr_nvpsiz = (cidr >> 8)&0x000F;
+ at91sam7_info->cidr_eproc = (cidr >> 5)&0x0007;
at91sam7_info->cidr_version = cidr&0x001F;
at91sam7_info->target_name = target_name;
at91sam7_protect_check(t_bank);
}
- LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch );
+ LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch);
return ERROR_OK;
}
}
/* Configure the flash controller timing */
- at91sam7_read_clock_info(bank);
+ at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
fast_check = 1;
- for (nSector=0; nSector<bank->num_sectors; nSector++)
+ for (nSector = 0; nSector < bank->num_sectors; nSector++)
{
- retval = target_blank_check_memory(target, bank->base+bank->sectors[nSector].offset,
+ retval = target_blank_check_memory(target, bank->base + bank->sectors[nSector].offset,
bank->sectors[nSector].size, &blank);
if (retval != ERROR_OK)
{
LOG_USER("Running slow fallback erase check - add working memory");
buffer = malloc(bank->sectors[0].size);
- for (nSector=0; nSector<bank->num_sectors; nSector++)
+ for (nSector = 0; nSector < bank->num_sectors; nSector++)
{
bank->sectors[nSector].is_erased = 1;
- retval = target_read_memory(target, bank->base+bank->sectors[nSector].offset, 4,
+ retval = target_read_memory(target, bank->base + bank->sectors[nSector].offset, 4,
bank->sectors[nSector].size/4, buffer);
if (retval != ERROR_OK)
return retval;
- for (nByte=0; nByte<bank->sectors[nSector].size; nByte++)
+ for (nByte = 0; nByte < bank->sectors[nSector].size; nByte++)
{
if (buffer[nByte] != 0xFF)
{
}
status = at91sam7_get_flash_status(bank->target, bank->bank_number);
- at91sam7_info->lockbits = (status>>16);
+ at91sam7_info->lockbits = (status >> 16);
at91sam7_info->num_lockbits_on = 0;
- for (lock_pos=0; lock_pos<bank->num_sectors; lock_pos++)
+ for (lock_pos = 0; lock_pos < bank->num_sectors; lock_pos++)
{
- if ( ((status>>(16+lock_pos))&(0x0001)) == 1)
+ if (((status >> (16 + lock_pos))&(0x0001)) == 1)
{
at91sam7_info->num_lockbits_on++;
bank->sectors[lock_pos].is_protected = 1;
/* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
status = at91sam7_get_flash_status(bank->target, 0);
- at91sam7_info->securitybit = (status>>4)&0x01;
- at91sam7_info->nvmbits = (status>>8)&0xFF;
+ at91sam7_info->securitybit = (status >> 4)&0x01;
+ at91sam7_info->nvmbits = (status >> 8)&0xFF;
at91sam7_info->num_nvmbits_on = 0;
- for (gpnvm_pos=0; gpnvm_pos<at91sam7_info->num_nvmbits; gpnvm_pos++)
+ for (gpnvm_pos = 0; gpnvm_pos < at91sam7_info->num_nvmbits; gpnvm_pos++)
{
- if ( ((status>>(8+gpnvm_pos))&(0x01)) == 1)
+ if (((status >> (8 + gpnvm_pos))&(0x01)) == 1)
{
at91sam7_info->num_nvmbits_on++;
}
return ERROR_OK;
}
-/***************************************************************************************************************************************************************************************
-# flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-# <ext_freq_khz> - MUST be used if clock is from external source
-# CAN be used if main oscillator frequency is known
-# Examples:
-# flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 25000 ==== RECOMENDED ============
-# flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 25000 (auto-detection, except for clock) ==== RECOMENDED ============
-# flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 0 ==== NOT RECOMENDED !!! ====
-# flash bank at91sam7 0 0 0 0 0 (old style, full auto-detection) ==== NOT RECOMENDED !!! ====
-****************************************************************************************************************************************************************************************/
static int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
{
flash_bank_t *t_bank = bank;
page_size = atoi(args[11]);
num_nvmbits = atoi(args[12]);
- target_name = calloc(strlen(args[7])+1, sizeof(char));
+ target_name = calloc(strlen(args[7]) + 1, sizeof(char));
strcpy(target_name, args[7]);
/* calculate bank size */
bank_size = num_sectors * pages_per_sector * page_size;
- for (bnk=0; bnk<banks_num; bnk++)
+ for (bnk = 0; bnk < banks_num; bnk++)
{
if (bnk > 0)
{
/* allocate sectors */
t_bank->sectors = malloc(num_sectors * sizeof(flash_sector_t));
- for (sec=0; sec<num_sectors; sec++)
+ for (sec = 0; sec < num_sectors; sec++)
{
t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
t_bank->sectors[sec].size = pages_per_sector * page_size;
if (erase_all)
{
- if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
+ if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
{
return ERROR_FLASH_OPERATION_FAILED;
}
/* allocate and clean buffer */
nbytes = (last - first + 1) * bank->sectors[first].size;
buffer = malloc(nbytes * sizeof(uint8_t));
- for (pos=0; pos<nbytes; pos++)
+ for (pos = 0; pos < nbytes; pos++)
{
buffer[pos] = 0xFF;
}
- if ( at91sam7_write(bank, buffer, bank->sectors[first].offset, nbytes) != ERROR_OK)
+ if (at91sam7_write(bank, buffer, bank->sectors[first].offset, nbytes) != ERROR_OK)
{
return ERROR_FLASH_OPERATION_FAILED;
}
}
/* mark erased sectors */
- for (sec=first; sec<=last; sec++)
+ for (sec = first; sec <= last; sec++)
{
bank->sectors[sec].is_erased = 1;
}
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
- for (sector=first; sector<=last; sector++)
+ for (sector = first; sector <= last; sector++)
{
if (set)
cmd = SLB;
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
- for (pagen=first_page; pagen<last_page; pagen++)
+ for (pagen = first_page; pagen < last_page; pagen++)
{
- if (bytes_remaining<dst_min_alignment)
+ if (bytes_remaining < dst_min_alignment)
count = bytes_remaining;
else
count = dst_min_alignment;
/* Write one block to the PageWriteBuffer */
buffer_pos = (pagen-first_page)*dst_min_alignment;
wcount = CEIL(count,4);
- if ((retval = target_write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos)) != ERROR_OK)
+ if ((retval = target_write_memory(target, bank->base + pagen*dst_min_alignment, 4, wcount, buffer + buffer_pos)) != ERROR_OK)
{
return retval;
}
buf += printed;
buf_size -= printed;
- printed = snprintf(buf,
+ printed = snprintf(buf,
buf_size,
" Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8" PRIx32 "\n",
- at91sam7_info->cidr,
- at91sam7_info->cidr_arch,
+ at91sam7_info->cidr,
+ at91sam7_info->cidr_arch,
EPROC[at91sam7_info->cidr_eproc],
- at91sam7_info->cidr_version,
+ at91sam7_info->cidr_version,
bank->size);
buf += printed;
return ERROR_OK;
}
-/*
-* On AT91SAM7S: When the gpnvm bits are set with
+/*
+* On AT91SAM7S: When the gpnvm bits are set with
* > at91sam7 gpnvm bitnr set
-* the changes are not visible in the flash controller status register MC_FSR
+* the changes are not visible in the flash controller status register MC_FSR
* until the processor has been reset.
* On the Olimex board this requires a power cycle.
* Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
if (argc != 2)
{
- command_print(cmd_ctx, "at91sam7 gpnvm <bit> <set|clear>");
+ command_print(cmd_ctx, "at91sam7 gpnvm <bit> <set | clear>");
return ERROR_OK;
}
/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
-
+
if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
{
return ERROR_FLASH_OPERATION_FAILED;
/* check protect state */
at91sam7_protect_check(bank);
-
+
return ERROR_OK;
}
Code Review / openocd.git / blobdiff