static uint32_t at91sam7_get_flash_status(target_t *target, int bank_number);
static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode);
static uint32_t at91sam7_wait_status_busy(flash_bank_t *bank, uint32_t waitbits, int timeout);
-static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen);
+static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen);
static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
flash_driver_t at91sam7_flash =
static long SRAMSIZ[16] = {
-1,
0x0400, /* 1K */
- 0x0800, /* 2K */
- -1,
+ 0x0800, /* 2K */
+ -1,
0x1c000, /* 112K */
0x1000, /* 4K */
0x14000, /* 80K */
target_read_u32(target, PMC_MCKR, &mckr);
/* Read Clock Generator PLL Register */
target_read_u32(target, CKGR_PLLR, &pllr);
-
+
at91sam7_info->mck_valid = 0;
at91sam7_info->mck_freq = 0;
- switch (mckr & PMC_MCKR_CSS)
+ switch (mckr & PMC_MCKR_CSS)
{
case 0: /* Slow Clock */
at91sam7_info->mck_valid = 1;
break;
case 1: /* Main Clock */
- if ((mcfr & CKGR_MCFR_MAINRDY) &&
+ if ((mcfr & CKGR_MCFR_MAINRDY) &&
(at91sam7_info->ext_freq == 0))
{
at91sam7_info->mck_valid = 1;
break;
case 3: /* PLL Clock */
- if ((mcfr & CKGR_MCFR_MAINRDY) &&
- (at91sam7_info->ext_freq == 0))
+ if ((mcfr & CKGR_MCFR_MAINRDY) &&
+ (at91sam7_info->ext_freq == 0))
{
target_read_u32(target, CKGR_PLLR, &pllr);
if (!(pllr & CKGR_PLLR_DIV))
}
/* Prescaler adjust */
- if ( (((mckr & PMC_MCKR_PRES) >> 2) == 7) || (tmp == 0) )
+ if ((((mckr & PMC_MCKR_PRES) >> 2) == 7) || (tmp == 0))
{
at91sam7_info->mck_valid = 0;
at91sam7_info->mck_freq = 0;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
- fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
+ fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
target_write_u32(target, MC_FCR[bank->bank_number], fcr);
LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number + 1, pagen);
return ERROR_OK;
}
- if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
+ if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
{
return ERROR_FLASH_OPERATION_FAILED;
}
at91sam7_protect_check(t_bank);
}
- LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch );
+ LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch);
return ERROR_OK;
}
}
/* Configure the flash controller timing */
- at91sam7_read_clock_info(bank);
+ at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
fast_check = 1;
at91sam7_info->num_lockbits_on = 0;
for (lock_pos = 0; lock_pos < bank->num_sectors; lock_pos++)
{
- if ( ((status >> (16 + lock_pos))&(0x0001)) == 1)
+ if (((status >> (16 + lock_pos))&(0x0001)) == 1)
{
at91sam7_info->num_lockbits_on++;
bank->sectors[lock_pos].is_protected = 1;
at91sam7_info->num_nvmbits_on = 0;
for (gpnvm_pos = 0; gpnvm_pos < at91sam7_info->num_nvmbits; gpnvm_pos++)
{
- if ( ((status >> (8 + gpnvm_pos))&(0x01)) == 1)
+ if (((status >> (8 + gpnvm_pos))&(0x01)) == 1)
{
at91sam7_info->num_nvmbits_on++;
}
if (erase_all)
{
- if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
+ if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
{
return ERROR_FLASH_OPERATION_FAILED;
}
buffer[pos] = 0xFF;
}
- if ( at91sam7_write(bank, buffer, bank->sectors[first].offset, nbytes) != ERROR_OK)
+ if (at91sam7_write(bank, buffer, bank->sectors[first].offset, nbytes) != ERROR_OK)
{
return ERROR_FLASH_OPERATION_FAILED;
}
buf += printed;
buf_size -= printed;
- printed = snprintf(buf,
+ printed = snprintf(buf,
buf_size,
" Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8" PRIx32 "\n",
- at91sam7_info->cidr,
- at91sam7_info->cidr_arch,
+ at91sam7_info->cidr,
+ at91sam7_info->cidr_arch,
EPROC[at91sam7_info->cidr_eproc],
- at91sam7_info->cidr_version,
+ at91sam7_info->cidr_version,
bank->size);
buf += printed;
return ERROR_OK;
}
-/*
-* On AT91SAM7S: When the gpnvm bits are set with
+/*
+* On AT91SAM7S: When the gpnvm bits are set with
* > at91sam7 gpnvm bitnr set
-* the changes are not visible in the flash controller status register MC_FSR
+* the changes are not visible in the flash controller status register MC_FSR
* until the processor has been reset.
* On the Olimex board this requires a power cycle.
* Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
-
+
if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
{
return ERROR_FLASH_OPERATION_FAILED;
/* check protect state */
at91sam7_protect_check(bank);
-
+
return ERROR_OK;
}