@c %**start of header
@setfilename openocd.info
@settitle Open On-Chip Debugger (openocd)
+@dircategory Development
+@direntry
+* OpenOCD: (openocd). Open On-Chip Debugger.
+@end direntry
@c %**end of header
@include version.texi
+@copying
+Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
+@quotation
+Permission is granted to copy, distribute and/or modify this document
+under the terms of the GNU Free Documentation License, Version 1.2 or
+any later version published by the Free Software Foundation; with no
+Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
+Texts. A copy of the license is included in the section entitled ``GNU
+Free Documentation License''.
+@end quotation
+@end copying
+
@titlepage
@title Open On-Chip Debugger (openocd)
@subtitle Edition @value{EDITION} for openocd version @value{VERSION}
@subtitle @value{UPDATED}
@page
@vskip 0pt plus 1filll
+@insertcopying
@end titlepage
@contents
@node Top, About, , (dir)
@top OpenOCD
-This is edition @value{EDITION} of the openocd manual for version
-@value{VERSION}, @value{UPDATED}
+This manual documents edition @value{EDITION} of the Open On-Chip Debugger
+(openocd) version @value{VERSION}, @value{UPDATED}.
+
+@insertcopying
@menu
* About:: About Openocd.
-* Developers::
+* Developers:: Openocd developers
* Building:: Building Openocd
* Running:: Running Openocd
* Configuration:: Openocd Configuration.
* Commands:: Openocd Commands
* Sample Scripts:: Sample Target Scripts
* GDB and Openocd:: Using GDB and Openocd
+* Upgrading:: Deprecated/Removed Commands
* FAQ:: Frequently Asked Questions
* License:: GNU Free Documentation License
* Index:: Main index.
current directory):
@smallexample
- svn checkout svn://svn.berlios.de/openocd/trunk
+ svn checkout svn://svn.berlios.de/openocd/trunk openocd
@end smallexample
Building the OpenOCD requires a recent version of the GNU autotools.
@smallexample
./configure
@end smallexample
-Configure generates the Makefiles used to build OpenOCD
+Configure generates the Makefiles used to build OpenOCD.
@smallexample
make
@end smallexample
-Make builds the OpenOCD, and places the final executable in ./src/
+Make builds the OpenOCD, and places the final executable in ./src/.
The configure script takes several options, specifying which JTAG interfaces
should be included:
@itemize @bullet
@item
---enable-parport
+@option{--enable-parport}
+@item
+@option{--enable-parport_ppdev}
@item
---enable-parport_ppdev
+@option{--enable-parport_giveio}
@item
---enable-amtjtagaccel
+@option{--enable-amtjtagaccel}
@item
---enable-ft2232_ftd2xx
+@option{--enable-ft2232_ftd2xx}
@footnote{Using the latest D2XX drivers from FTDI and following their installation
instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
-build properly}
+build properly.}
+@item
+@option{--enable-ft2232_libftdi}
+@item
+@option{--with-ftd2xx=/path/to/d2xx/}
@item
---enable-ft2232_libftdi
+@option{--enable-gw16012}
@item
---with-ftd2xx=/path/to/d2xx/
+@option{--enable-usbprog}
+@item
+@option{--enable-presto_libftdi}
+@item
+@option{--enable-presto_ftd2xx}
@end itemize
If you want to access the parallel port using the PPDEV interface you have to specify
@node Running
@chapter Running
@cindex running openocd
+@cindex --configfile
+@cindex --debug_level
+@cindex --logfile
+@cindex --search
The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
Run with @option{--help} or @option{-h} to view the available command line arguments.
only informational messages, warnings and errors. You can also change this setting
from within a telnet or gdb session (@option{debug_level <n>}).
-You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
+You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
+
+Search paths for config/script files can be added to openocd by using
+the @option{-s <search>} switch.
@node Configuration
@chapter Configuration
Set to <@var{enable}> so that openocd will program the flash memory when a
vFlash packet is received.
Default behaviour is <@var{disable}>
-@item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
+@item @b{daemon_startup} <@var{mode}>
@cindex daemon_startup
+@option{mode} can either @option{attach} or @option{reset}
Tells the OpenOCD whether it should reset the target when the daemon is launched, or
if it should just attach to the target.
@end itemize
Use the interface driver <@var{name}> to connect to the target. Currently supported
interfaces are
@itemize @minus
-@item parport
+@item @b{parport}
PC parallel port bit-banging (Wigglers, PLD download cable, ...)
@end itemize
@itemize @minus
-@item amt_jtagaccel
+@item @b{amt_jtagaccel}
Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
mode parallel port
@end itemize
@itemize @minus
-@item ft2232
+@item @b{ft2232}
FTDI FT2232 based devices using either the open-source libftdi or the binary only
FTD2XX driver. The FTD2XX is superior in performance, but not available on every
platform. The libftdi uses libusb, and should be portable to all systems that provide
libusb.
@end itemize
@itemize @minus
-@item ep93xx
+@item @b{ep93xx}
Cirrus Logic EP93xx based single-board computer bit-banging (in development)
@end itemize
+@itemize @minus
+@item @b{presto}
+ASIX PRESTO USB JTAG programmer.
+@end itemize
+@itemize @minus
+@item @b{usbprog}
+usbprog is a freely programmable USB adapter.
+@end itemize
+@itemize @minus
+@item @b{gw16012}
+Gateworks GW16012 JTAG programmer.
+@end itemize
@end itemize
@itemize @bullet
-@item @b{jtag_speed} <@var{number}>
+@item @b{jtag_speed} <@var{reset speed}> <@var{post reset speed}>
@cindex jtag_speed
Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
-speed. The actual effect of this option depends on the JTAG interface used.
-
+speed. The actual effect of this option depends on the JTAG interface used. Reset
+speed is used during reset and post reset speed after reset. post reset speed
+is optional, in which case the reset speed is used.
@itemize @minus
+
@item wiggler: maximum speed / @var{number}
@item ft2232: 6MHz / (@var{number}+1)
@item amt jtagaccel: 8 / 2**@var{number}
Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
especially true for synthesized cores (-S).
+@item @b{jtag_khz} <@var{reset speed kHz}> <@var{post reset speed kHz}>
+@cindex jtag_khz
+Same as jtag_speed, except that the speed is specified in maximum kHz. If
+the device can not support the rate asked for, or can not translate from
+kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
+is not supported, then an error is reported.
+
@item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
@cindex reset_config
The configuration of the reset signals available on the JTAG interface AND the target.
If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
-then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
-@samp{srst_only} or @samp{trst_and_srst}.
+then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
+@option{srst_only} or @option{trst_and_srst}.
+
[@var{combination}] is an optional value specifying broken reset signal implementations.
-@samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
-the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
+@option{srst_pulls_trst} states that the testlogic is reset together with the reset of
+the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
that the system is reset together with the test logic (only hypothetical, I haven't
seen hardware with such a bug, and can be worked around).
+@option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
+The default behaviour if no option given is @option{separate}.
The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
-reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
-and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
-(default) and @samp{srst_push_pull} for the system reset. These values only affect
+reset lines to be specified. Possible values are @option{trst_push_pull} (default)
+and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
+(default) and @option{srst_push_pull} for the system reset. These values only affect
JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
@item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
The layout of the parallel port cable used to connect to the target.
Currently supported cables are
@itemize @minus
-@item wiggler
+@item @b{wiggler}
@cindex wiggler
Original Wiggler layout, also supported by several clones, such
as the Olimex ARM-JTAG
-@item old_amt_wiggler
+@item @b{old_amt_wiggler}
@cindex old_amt_wiggler
The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
version available from the website uses the original Wiggler layout ('@var{wiggler}')
-@item chameleon
+@item @b{chameleon}
@cindex chameleon
Describes the connection of the Amontec Chameleon's CPLD when operated in
configuration mode. This is only used to program the Chameleon itself, not
a connected target.
-@item dlc5
+@item @b{dlc5}
@cindex dlc5
Xilinx Parallel cable III.
-@item triton
+@item @b{triton}
@cindex triton
The parallel port adapter found on the 'Karo Triton 1 Development Board'.
This is also the layout used by the HollyGates design
(see @uref{http://www.lartmaker.nl/projects/jtag/}).
-@item flashlink
+@item @b{flashlink}
@cindex flashlink
ST Parallel cable.
@end itemize
The layout of the FT2232 GPIO signals used to control output-enables and reset
signals. Valid layouts are
@itemize @minus
-@item usbjtag
+@item @b{usbjtag}
The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
-@item jtagkey
+@item @b{jtagkey}
Amontec JTAGkey and JTAGkey-tiny
-@item signalyzer
+@item @b{signalyzer}
Signalyzer
-@item olimex-jtag
+@item @b{olimex-jtag}
Olimex ARM-USB-OCD
-@item m5960
+@item @b{m5960}
American Microsystems M5960
-@item evb_lm3s811
+@item @b{evb_lm3s811}
Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
SRST signals on external connector
-@item comstick
+@item @b{comstick}
Hitex STR9 comstick
-@item stm32stick
+@item @b{stm32stick}
Hitex STM32 Performance Stick
-@item flyswatter
+@item @b{flyswatter}
Tin Can Tools Flyswatter
-@item turtelizer2
+@item @b{turtelizer2}
egnite Software turtelizer2
-@item oocdlink
+@item @b{oocdlink}
OOCDLink
@end itemize
@cindex target
Defines a target that should be debugged. Currently supported types are:
@itemize @minus
-@item arm7tdmi
-@item arm720t
-@item arm9tdmi
-@item arm920t
-@item arm922t
-@item arm926ejs
-@item arm966e
-@item cortex_m3
-@item xscale
+@item @b{arm7tdmi}
+@item @b{arm720t}
+@item @b{arm9tdmi}
+@item @b{arm920t}
+@item @b{arm922t}
+@item @b{arm926ejs}
+@item @b{arm966e}
+@item @b{cortex_m3}
+@item @b{feroceon}
+@item @b{xscale}
@end itemize
If you want to use a target board that is not on this list, see Adding a new
The reset_mode specifies what should happen to the target when a reset occurs:
@itemize @minus
-@item reset_halt
+@item @b{reset_halt}
@cindex reset_halt
Immediately request a target halt after reset. This allows targets to be debugged
from the very first instruction. This is only possible with targets and JTAG
interfaces that correctly implement the reset signals.
-@item reset_init
+@item @b{reset_init}
@cindex reset_init
Similar to @option{reset_halt}, but executes the script file defined to handle the
'reset' event for the target. Like @option{reset_halt} this only works with
correct reset implementations.
-@item reset_run
+@item @b{reset_run}
@cindex reset_run
Simply let the target run after a reset.
-@item run_and_halt
+@item @b{run_and_halt}
@cindex run_and_halt
Let the target run for some time (default: 1s), and then request halt.
-@item run_and_init
+@item @b{run_and_init}
@cindex run_and_init
A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
to run for some time, then halted, and the @option{reset} event script is executed.
This optional parameter overwrites the setting specified in the configuration file,
making the new behaviour the default for the @option{reset} command.
@itemize @minus
-@item run
+@item @b{run}
@cindex reset run
Let the target run.
-@item halt
+@item @b{halt}
@cindex reset halt
Immediately halt the target (works only with certain configurations).
-@item init
+@item @b{init}
@cindex reset init
Immediately halt the target, and execute the reset script (works only with certain
configurations)
-@item run_and_halt
+@item @b{run_and_halt}
@cindex reset run_and_halt
Let the target run for a certain amount of time, then request a halt.
-@item run_and_init
+@item @b{run_and_init}
@cindex reset run_and_init
Let the target run for a certain amount of time, then request a halt. Execute the
reset script once the target entered debug mode.
@cindex verify_image
Verify <@var{file}> to target memory starting at <@var{address}>.
This will first attempt using a crc checksum, if this fails it will try a binary compare.
-@item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
-@cindex load_binary
-Load binary <@var{file}> to target memory at <@var{address}>
-@item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
-@cindex dump_binary
-Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
-(binary) <@var{file}>.
@end itemize
@subsection Flash commands
@item @b{flash protect_check} <@var{num}>
@cindex flash protect_check
Check protection state of sectors in flash bank <num>.
-
-@item @b{flash erase} <@var{num}> <@var{first}> <@var{last}> [DEPRECATED]
-@cindex flash erase
-Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
-<@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
-require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
-the CFI driver). This command was replaced by the new command
@option{flash erase_sector} using the same syntax.
@item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
@cindex flash erase_sector
@item @b{flash erase_address} <@var{address}> <@var{length}>
@cindex flash erase_address
Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
-@item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
-@cindex flash write
-Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
-bytes from the beginning of the bank. This command was replaced by the new command
-@option{flash write_binary} using the same syntax.
-@item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
-@cindex flash write_binary
+@item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
+@cindex flash write_bank
Write the binary <@var{file}> to flash bank <@var{num}>, starting at
-<@option{offset}> bytes from the beginning of the bank.
+<@option{offset}> bytes from the beginning of the bank.
@item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
@cindex flash write_image
Write the image <@var{file}> to the current target's flash bank(s). A relocation
[@var{offset}] can be specified and the file [@var{type}] can be specified
explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
-(ELF file) or @option{s19} (Motorola s19).
+(ELF file) or @option{s19} (Motorola s19).
@item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
@cindex flash protect
Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
Display a list of all banked core registers, fetching the current value from every
core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
register value.
-@item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
+@item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
@cindex armv4_5 core_mode
Displays the core_mode, optionally changing it to either ARM or Thumb mode.
The target is resumed in the currently set @option{core_mode}.
These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
ARM920t or ARM926EJ-S.
@itemize @bullet
-@item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
+@item @b{arm7_9 sw_bkpts} <@var{enable}|@var{disable}>
@cindex arm7_9 sw_bkpts
Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
one of the watchpoint registers to implement software breakpoints. Disabling
SW Bkpts frees that register again.
-@item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
+@item @b{arm7_9 force_hw_bkpts} <@var{enable}|@var{disable}>
@cindex arm7_9 force_hw_bkpts
When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
breakpoints are turned into hardware breakpoints.
-@item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
+@item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
@cindex arm7_9 dbgrq
Enable use of the DBGRQ bit to force entry into debug mode. This should be
safe for all but ARM7TDMI--S cores (like Philips LPC).
-@item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
-@cindex arm7_9 fast_writes [DEPRECATED]
-See @option{arm7_9 fast_memory_access} instead.
-@item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
+@item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
@cindex arm7_9 fast_memory_access
Allow the OpenOCD to read and write memory without checking completion of
the operation. This provides a huge speed increase, especially with USB JTAG
cables (FT2232), but might be unsafe if used with targets running at a very low
speed, like the 32kHz startup clock of an AT91RM9200.
-@item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
+@item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
@cindex arm7_9 dcc_downloads
Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
with OpenOCD rev. 60.
@end itemize
+@subsection ARM720T specific commands
+@cindex ARM720T specific commands
+
+@itemize @bullet
+@item @b{arm720t cp15} <@var{num}> [@var{value}]
+@cindex arm720t cp15
+display/modify cp15 register <@option{num}> [@option{value}].
+@item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
+@cindex arm720t md<bhw>_phys
+Display memory at physical address addr.
+@item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
+@cindex arm720t mw<bhw>_phys
+Write memory at physical address addr.
+@item @b{arm720t virt2phys} <@var{va}>
+@cindex arm720t virt2phys
+Translate a virtual address to a physical address.
+@end itemize
+
+@subsection ARM9TDMI specific commands
+@cindex ARM9TDMI specific commands
+
+@itemize @bullet
+@item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
+@cindex arm9tdmi vector_catch
+Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
+@option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
+@option{irq} @option{fiq}.
+
+Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
+@end itemize
+
+@subsection ARM966E specific commands
+@cindex ARM966E specific commands
+
+@itemize @bullet
+@item @b{arm966e cp15} <@var{num}> [@var{value}]
+@cindex arm966e cp15
+display/modify cp15 register <@option{num}> [@option{value}].
+@end itemize
+
@subsection ARM920T specific commands
@cindex ARM920T specific commands
@itemize @bullet
+@item @b{arm920t cp15} <@var{num}> [@var{value}]
+@cindex arm920t cp15
+display/modify cp15 register <@option{num}> [@option{value}].
+@item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
+@cindex arm920t cp15i
+display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
@item @b{arm920t cache_info}
@cindex arm920t cache_info
Print information about the caches found. This allows you to see if your target
@item @b{arm920t read_mmu} <@var{filename}>
@cindex arm920t read_mmu
Dump the content of the ITLB and DTLB to a file.
-@item @b{arm920t virt2phys} <@var{VA}>
+@item @b{arm920t virt2phys} <@var{va}>
@cindex arm920t virt2phys
Translate a virtual address to a physical address.
@end itemize
+@subsection ARM926EJS specific commands
+@cindex ARM926EJS specific commands
+
+@itemize @bullet
+@item @b{arm926ejs cp15} <@var{num}> [@var{value}]
+@cindex arm926ejs cp15
+display/modify cp15 register <@option{num}> [@option{value}].
+@item @b{arm926ejs cache_info}
+@cindex arm926ejs cache_info
+Print information about the caches found.
+@item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
+@cindex arm926ejs md<bhw>_phys
+Display memory at physical address addr.
+@item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
+@cindex arm926ejs mw<bhw>_phys
+Write memory at physical address addr.
+@item @b{arm926ejs virt2phys} <@var{va}>
+@cindex arm926ejs virt2phys
+Translate a virtual address to a physical address.
+@end itemize
+
@page
@section Debug commands
@cindex Debug commands
@item @b{scan_chain}
@cindex scan_chain
Print current scan chain configuration.
-@item @b{jtag_reset}
+@item @b{jtag_reset} <@var{trst}> <@var{srst}>
@cindex jtag_reset
-Toggle reset lines <@var{trst}> <@var{srst}>.
+Toggle reset lines.
@item @b{endstate} <@var{tap_state}>
@cindex endstate
Finish JTAG operations in <@var{tap_state}>.
@item @b{statemove} [@var{tap_state}]
@cindex statemove
Move to current endstate or [@var{tap_state}]
-@item @b{irscan}
+@item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
@cindex irscan
Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
-@item @b{drscan}
+@item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
@cindex drscan
Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
-@item @b{verify_ircapture}
+@item @b{verify_ircapture} <@option{enable}|@option{disable}>
@cindex verify_ircapture
-Verify value captured during Capture-IR <@option{enable}|@option{disable}>
-@item @b{var}
+Verify value captured during Capture-IR. Default is enabled.
+@item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
@cindex var
Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
-@item @b{field}
+@item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
@cindex field
-Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
+Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
+@end itemize
+
+@page
+@section Target Requests
+@cindex Target Requests
+Openocd can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
+See libdcc in the contrib dir for more details.
+@itemize @bullet
+@item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
+@cindex target_request debugmsgs
+Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
@end itemize
@node Sample Scripts
@section STR71x Script
@cindex STR71x Script
-The following script was used with an Amontec JTAGkey and a STR710 / STR711 cpu:
+The following script was used with an Amontec JTAGkey and a STR710 / STR711 CPU:
@smallexample
#daemon configuration
telnet_port 4444
@section STR750 Script
@cindex STR750 Script
-The following script was used with an Amontec JTAGkey and a STR750 cpu:
+The following script was used with an Amontec JTAGkey and a STR750 CPU:
@smallexample
#daemon configuration
telnet_port 4444
@section STR912 Script
@cindex STR912 Script
-The following script was used with an Amontec JTAGkey and a STR912 cpu:
+The following script was used with an Amontec JTAGkey and a STR912 CPU:
@smallexample
#daemon configuration
telnet_port 4444
@section STM32x Script
@cindex STM32x Script
-The following script was used with an Amontec JTAGkey and a STM32x cpu:
+The following script was used with an Amontec JTAGkey and a STM32x CPU:
@smallexample
#daemon configuration
telnet_port 4444
@section LPC2129 Script
@cindex LPC2129 Script
-The following script was used with an wiggler PP and a LPC-2129 cpu:
+The following script was used with an wiggler PP and a LPC-2129 CPU:
@smallexample
#daemon configuration
telnet_port 4444
@section LPC2148 Script
@cindex LPC2148 Script
-The following script was used with an Amontec JTAGkey and a LPC2148 cpu:
+The following script was used with an Amontec JTAGkey and a LPC2148 CPU:
@smallexample
#daemon configuration
telnet_port 4444
@section LPC2294 Script
@cindex LPC2294 Script
-The following script was used with an Amontec JTAGkey and a LPC2294 cpu:
+The following script was used with an Amontec JTAGkey and a LPC2294 CPU:
@smallexample
#daemon configuration
telnet_port 4444
@section AT91R40008 Script
@cindex AT91R40008 Script
-The following script was used with an Amontec JTAGkey and a AT91R40008 cpu:
+The following script was used with an Amontec JTAGkey and a AT91R40008 CPU:
@smallexample
#daemon configuration
telnet_port 4444
@section AT91SAM7s Script
@cindex AT91SAM7s Script
-The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 cpu:
+The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 CPU:
@smallexample
#daemon configuration
telnet_port 4444
@section XSCALE IXP42x Script
@cindex XSCALE IXP42x Script
-The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x cpu:
+The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x CPU:
@smallexample
#daemon configuration
telnet_port 4444
@section Hilscher netX 100 / 500 Script
@cindex Hilscher netX 100 / 500 Script
The following script was used with an Amontec JTAGkey and a Hilscher
-netX 500 cpu:
+netX 500 CPU:
@smallexample
#daemon configuration
telnet_port 4444
using a memory map.
To view the configured memory map in gdb, use the gdb command @option{info mem}
-All other unasigned addresses within gdb are treated as ram.
+All other unasigned addresses within gdb are treated as RAM.
+
+GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
+this can be changed to the old behaviour by using the following gdb command.
+@smallexample
+set mem inaccessible-by-default off
+@end smallexample
If @option{gdb_flash_program enable} is also used, gdb will be able to
program any flash memory using the vFlash interface.
To verify any flash programming the gdb command @option{compare-sections}
can be used.
+@node Upgrading
+@chapter Deprecated/Removed Commands
+@cindex Deprecated/Removed Commands
+Certain openocd commands have been deprecated/removed during the various revisions.
+
+@itemize @bullet
+@item @b{load_binary}
+@cindex load_binary
+use @option{load_image} command with same args
+@item @b{dump_binary}
+@cindex dump_binary
+use @option{dump_image} command with same args
+@item @b{flash erase}
+@cindex flash erase
+use @option{flash erase_sector} command with same args
+@item @b{flash write}
+@cindex flash write
+use @option{flash write_bank} command with same args
+@item @b{flash write_binary}
+@cindex flash write_binary
+use @option{flash write_bank} command with same args
+@item @b{arm7_9 fast_writes}
+@cindex arm7_9 fast_writes
+use @option{arm7_9 fast_memory_access} command with same args
+@end itemize
+
@node FAQ
@chapter FAQ
@cindex faq
@enumerate
-@item OpenOCD complains about a missing cygwin1.dll
+@item OpenOCD complains about a missing cygwin1.dll.
Make sure you have Cygwin installed, or at least a version of OpenOCD that
claims to come with all the necessary dlls. When using Cygwin, try launching
GDB issues software breakpoints when a normal breakpoint is requested, or to implement
source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
software breakpoints consume one of the two available hardware breakpoints,
-and are therefor disabled by default. If your code is running from RAM, you
+and are therefore disabled by default. If your code is running from RAM, you
can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
your code resides in Flash, you can't use software breakpoints, but you can force
OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
out while waiting for end of scan, rtck was disabled".
Make sure your PC's parallel port operates in EPP mode. You might have to try several
-settings in your PC Bios (ECP, EPP, and different versions of those).
+settings in your PC BIOS (ECP, EPP, and different versions of those).
@item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
unstable. When single-stepping over large blocks of code, GDB and OpenOCD
quit with an error message. Is there a stability issue with OpenOCD?
-No, this is not a stability issue concering OpenOCD. Most users have solved
-this issue by simply using a self-powered USB Hub, which they connect their
+No, this is not a stability issue concerning OpenOCD. Most users have solved
+this issue by simply using a self-powered USB hub, which they connect their
Amontec JTAGkey to. Apparently, some computers do not provide a USB power
supply stable enough for the Amontec JTAGkey to be operated.
First of all, the reason might be the USB power supply. Try using a self-powered
hub instead of a direct connection to your computer. Secondly, the error code 4
corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
-Chip ran into some sort of error - this points us to a USB problem.
+chip ran into some sort of error - this points us to a USB problem.
@item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
@item In the configuration file in the section where flash device configurations
are described, there is a parameter for specifying the clock frequency for
LPC2000 internal flash devices (e.g.
-@option{flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14746 calc_checksum}),
-which must be sepcified in kilohertz. However, I do have a quartz crystal of a
+@option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
+which must be specified in kilohertz. However, I do have a quartz crystal of a
frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
Is it possible to specify real numbers for the clock frequency?
@item Sometimes my debugging session terminates with an error. When I look into the
log file, I can see these error messages: Error: arm7_9_common.c:561
arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
+
+TODO.
@end enumerate
Code Review / openocd.git / blobdiff