MIPS: update arch_info access to match other targets

[openocd.git] / doc / openocd.texi

diff --git a/doc/openocd.texi b/doc/openocd.texi
index bf7402d43827f524959f1a58f29eccf4b7070846..47951c6d777393d1dd396bbb007a393d48765c2e 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -223,7 +223,7 @@ communication between developers:
 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
 
 Discuss and submit patches to this list.
-The @file{PATCHES} file contains basic information about how
+The @file{PATCHES.txt} file contains basic information about how
 to prepare patches.
 
 
@@ -1721,17 +1721,17 @@ In such cases, just specify the relevant port number as zero.
 If you disable all access through TCP/IP, you will need to
 use the command line @option{-pipe} option.
 
-@deffn {Command} gdb_port (number)
+@deffn {Command} gdb_port [number]
 @cindex GDB server
 Specify or query the first port used for incoming GDB connections.
 The GDB port for the
 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
 When not specified during the configuration stage,
 the port @var{number} defaults to 3333.
-When specified as zero, this port is not activated.
+When specified as zero, GDB remote access ports are not activated.
 @end deffn
 
-@deffn {Command} tcl_port (number)
+@deffn {Command} tcl_port [number]
 Specify or query the port used for a simplified RPC
 connection that can be used by clients to issue TCL commands and get the
 output from the Tcl engine.
@@ -1741,7 +1741,7 @@ the port @var{number} defaults to 6666.
 When specified as zero, this port is not activated.
 @end deffn
 
-@deffn {Command} telnet_port (number)
+@deffn {Command} telnet_port [number]
 Specify or query the
 port on which to listen for incoming telnet connections.
 This port is intended for interaction with one human through TCL commands.
@@ -4673,7 +4673,7 @@ NAND chips must be declared in configuration scripts,
 plus some additional configuration that's done after
 OpenOCD has initialized.
 
-@deffn {Config Command} {nand device} name controller target [configparams...]
+@deffn {Config Command} {nand device} name driver target [configparams...]
 Declares a NAND device, which can be read and written to
 after it has been configured through @command{nand probe}.
 In OpenOCD, devices are single chips; this is unlike some
@@ -4688,8 +4688,8 @@ configuration files, not interactively.
 
 @itemize @bullet
 @item @var{name} ... may be used to reference the NAND bank
-in other commands.
-@item @var{controller} ... identifies the controller driver
+in most other NAND commands.  A number is also available.
+@item @var{driver} ... identifies the NAND controller driver
 associated with the NAND device being declared.
 @xref{NAND Driver List}.
 @item @var{target} ... names the target used when issuing
@@ -6030,6 +6030,10 @@ and ARM9 commands.
 @deffn Command {arm966e cp15} regnum [value]
 Display cp15 register @var{regnum};
 else if a @var{value} is provided, that value is written to that register.
+The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
+ARM966E-S TRM.
+There is no current control over bits 31..30 from that table,
+as required for BIST support.
 @end deffn
 
 @subsection XScale specific commands
@@ -6105,7 +6109,7 @@ else if a @var{value} is provided, that value is written to that register.
 Changes the address used for the specified target's debug handler.
 @end deffn
 
-@deffn Command {xscale dcache} (@option{enable}|@option{disable})
+@deffn Command {xscale dcache} [@option{enable}|@option{disable}]
 Enables or disable the CPU's data cache.
 @end deffn
 
@@ -6113,17 +6117,18 @@ Enables or disable the CPU's data cache.
 Dumps the raw contents of the trace buffer to @file{filename}.
 @end deffn
 
-@deffn Command {xscale icache} (@option{enable}|@option{disable})
+@deffn Command {xscale icache} [@option{enable}|@option{disable}]
 Enables or disable the CPU's instruction cache.
 @end deffn
 
-@deffn Command {xscale mmu} (@option{enable}|@option{disable})
+@deffn Command {xscale mmu} [@option{enable}|@option{disable}]
 Enables or disable the CPU's memory management unit.
 @end deffn
 
-@deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
-Enables or disables the trace buffer,
-and controls how it is emptied.
+@deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
+Displays the trace buffer status, after optionally
+enabling or disabling the trace buffer
+and modifying how it is emptied.
 @end deffn
 
 @deffn Command {xscale trace_image} filename [offset [type]]
@@ -6155,7 +6160,7 @@ The mask bits correspond with bit 16..23 in the DCSR:
 @end deffn
 
 @anchor{xscale vector_table}
-@deffn Command {xscale vector_table} [<low|high> <index> <value>]
+@deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
 @cindex vector_table
 
 Set an entry in the mini-IC vector table. There are two tables: one for