+
+ /* enable any pending breakpoints and watchpoints */
+ xscale_enable_breakpoints(target);
+ xscale_enable_watchpoints(target);
+
+ /* restore banked registers */
+ xscale_restore_context(target);
+
+ /* send resume request (command 0x30 or 0x31)
+ * clean the trace buffer if it is to be enabled (0x62) */
+ if (xscale->trace.buffer_enabled)
+ {
+ xscale_send_u32(target, 0x62);
+ xscale_send_u32(target, 0x31);
+ }
+ else
+ xscale_send_u32(target, 0x30);
+
+ /* send CPSR */
+ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+ LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+
+ for (i = 7; i >= 0; i--)
+ {
+ /* send register */
+ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
+ LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
+ }
+
+ /* send PC */
+ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+ LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+
+ target->debug_reason = DBG_REASON_NOTHALTED;
+
+ if (!debug_execution)
+ {
+ /* registers are now invalid */
+ armv4_5_invalidate_core_regs(target);
+ target->state = TARGET_RUNNING;
+ target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+ }
+ else
+ {
+ target->state = TARGET_DEBUG_RUNNING;
+ target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
+ }
+
+ LOG_DEBUG("target resumed");
+
+ xscale->handler_running = 1;
+
+ return ERROR_OK;
+}
+
+static int xscale_step_inner(struct target_s *target, int current, u32 address, int handle_breakpoints)
+{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ xscale_common_t *xscale = armv4_5->arch_info;
+
+ u32 next_pc;
+ int retval;
+ int i;
+
+ target->debug_reason = DBG_REASON_SINGLESTEP;
+
+ /* calculate PC of next instruction */
+ if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
+ {
+ u32 current_opcode, current_pc;
+ current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+
+ target_read_u32(target, current_pc, ¤t_opcode);
+ LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
+ return retval;
+ }
+
+ LOG_DEBUG("enable single-step");
+ if ((retval=xscale_enable_single_step(target, next_pc))!=ERROR_OK)
+ return retval;
+